Abstract: Various systems and methods for USB Device-initiated data transfers and platform offload capabilities, and related processing and communication capabilities in a USB Host, are discussed. An example method for data offloading of data from a USB Device to a USB Host includes: receiving a data available notification from a USB Device connected to a USB Host via a USB interface; using a USB Host Controller to read buffered data from a buffer of the USB Device, in response to the data available notification; and providing the buffered data from the USB Host Controller to an Offload Engine of the USB Host.

Abstract: A Universal Serial Bus 4 (USB4) host system for tunneling USB2 data includes a USB controller and a first routing circuit communicatively coupled to the USB controller. The first routing circuit is to configure a downstream tunneled path between the USB controller and a second routing circuit. The first routing circuit is further to packetize outgoing USB2 data received from the USB controller into a first plurality of USB4 tunneled packets. The first routing circuit is further to encode the first plurality of USB4 tunneled packets for transmission to the second routing circuit via the downstream tunneled path, to initiate processing of the outgoing USB2 data by a USB2 device associated with the second routing circuit.

Abstract: A USB4 host system for offloading compute processing includes a host processor and a first routing circuit communicatively coupled to the host processor via an interface adapter. The first routing circuit is to decode device capability information received via a USB Type-C communication link from a second routing circuit. The device capability information indicates the second routing circuit is configured for offload processing. A downstream tunneled path is configured between the host processor and the second routing circuit based on the device capability information. The downstream tunneled path includes the USB Type-C communication link. One or more acceleration commands and operands/data from the host processor are packetized into a first plurality of USB4 tunneled packets. The first plurality of USB4 tunneled packets is encoded for transmission to the second routing circuit via the downstream tunneled path, to initiate the offload processing of the operands/data by the second routing circuit.

Abstract: Examples relate to apparatuses, devices, methods, computer programs and non-transitory computer-readable media for emulating clock stretching. A controller apparatus is configured to communicate with a target apparatus via a bus, and to emulate clock stretching based on requests to start and end clock stretching obtained via an in-band interrupt mechanism. The controller apparatus is configured to pause data or command transmissions to the target apparatus during the emulated clock stretching, and to resume the data or command transmissions to the target apparatus after the emulated clock stretching has ended.

Abstract: Provided is an apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to detect a connection of a peripheral device to an I/O connector of a plurality of I/O connectors connected to an SoC. The plurality of I/O connectors are configured to be coupled to a plurality of I/O controller ports of the SoC via a crossbar switch. The plurality of I/O controller ports are associated with an I/O performance level. At least two I/O controller ports have a different I/O performance level. The machine-readable instructions further include instructions to determine a target I/O controller port from the plurality of I/O controller ports for the peripheral device based on previous routing information for the peripheral device and to instruct the crossbar switch to electrically route the I/O connector to the determined target I/O controller port.

Abstract: Some aspects of the present disclosure relate to a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries, cause the one or more processing circuitries to perform a method for a computer system, comprising obtaining user input intended for a remote computer system, subdividing the user input into a plurality of discrete segments, processing the plurality of discrete segments to determine at least one segment that contains sensitive information according to a sensitivity criterion, replacing the at least one segment of the user input using synthetic information derived from the sensitive information, with the synthetic information derived from the sensitive information being less sensitive according to the sensitivity criterion, and providing the user input to the remote computer system.

Abstract: Various systems and methods for USB Device-initiated data transfers and platform offload capabilities, and related processing and communication capabilities in a USB Host, are discussed. An example method for data offloading of data from a USB Device to a USB Host includes: receiving a data available notification from a USB Device connected to a USB Host via a USB interface; using a USB Host Controller to read buffered data from a buffer of the USB Device, in response to the data available notification; and providing the buffered data from the USB Host Controller to an Offload Engine of the USB Host.

Abstract: A method, apparatus, and non-transitory computer-readable medium or reconfiguring an original active region of a first display is disclosed. The apparatus comprises interface circuitry for communication with both the first and second displays, memory circuitry, machine-readable instructions, and processor circuitry configured to execute the machine-readable instructions. The processor circuitry is operable to determine a subset active region within the original active region of the first display and to generate a hint for configuring the second display based on this subset active region.

Abstract: Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed example apparatus also control a device layer of the audio stack to enter a device layer low power mode in response to a first determination that the audio latency requirement(s) is/are met by the audio latency characteristic(s). Disclosed example apparatus further control a hardware layer of the audio stack to enter a hardware layer low power mode in response to the first determination and a second determination that an operation condition for entry into the hardware layer low power mode is met.

Abstract: For example, a debug target may include an interconnect interface; and a debug manager configured to cause the debug target to process a debug request message received from a Debug and Test System (DTS) via the interconnect interface. For example, the debug request message may include a group Identifier (ID) value and a debug request. For example, the debug manager may be configured to cause the debug target to execute the debug request, for example, based on a determination that the group ID value is to identify a group of debug targets including the debug target. For example, the debug manager may be configured to cause the debug target to send a debug response message via the interconnect interface, the debug response message including the group ID value and a debug response for the DTS.

Abstract: In one embodiment, a host processor includes a configuration circuit that, in response to identification of a first device capable of debugging a second device, is to configure a switch to enable device-to-device messaging between the first device and the second device, the device-to-device messaging comprising at least one of debug messaging or test messaging to be communicated without host processor involvement. Other embodiments are described and claimed.

Abstract: A Universal Serial Bus 4 (USB4) host system for tunneling USB2 data includes a USB controller and a first routing circuit communicatively coupled to the USB controller. The first routing circuit is to configure a downstream tunneled path between the USB controller and a second routing circuit. The first routing circuit is further to packetize outgoing USB2 data received from the USB controller into a first plurality of USB4 tunneled packets. The first routing circuit is further to encode the first plurality of USB4 tunneled packets for transmission to the second routing circuit via the downstream tunneled path, to initiate processing of the outgoing USB2 data by a USB2 device associated with the second routing circuit.

Abstract: A USB4 host system for offloading compute processing includes a host processor and a first routing circuit communicatively coupled to the host processor via an interface adapter. The first routing circuit is to decode device capability information received via a USB Type-C communication link from a second routing circuit. The device capability information indicates the second routing circuit is configured for offload processing. A downstream tunneled path is configured between the host processor and the second routing circuit based on the device capability information. The downstream tunneled path includes the USB Type-C communication link. One or more acceleration commands and operands/data from the host processor are packetized into a first plurality of USB4 tunneled packets. The first plurality of USB4 tunneled packets is encoded for transmission to the second routing circuit via the downstream tunneled path, to initiate the offload processing of the operands/data by the second routing circuit.

Abstract: Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed example apparatus also control a device layer of the audio stack to enter a device layer low power mode in response to a first determination that the audio latency requirement(s) is/are met by the audio latency characteristic(s). Disclosed example apparatus further control a hardware layer of the audio stack to enter a hardware layer low power mode in response to the first determination and a second determination that an operation condition for entry into the hardware layer low power mode is met.

Abstract: In one embodiment, an apparatus includes: a converter to receive and convert single-ended data to differential data, and receive and convert a single-ended clock signal to a differential clock signal; a multiplexer coupled to the converter to receive the differential data and the differential clock signal; and a controller coupled to the multiplexer. In response to an indication that a device coupled to the apparatus is capable of an alternate mode, the controller is to configure the multiplexer to send the differential data on at least one of a plurality of differential pairs of data lanes. Other embodiments are described and claimed.