Abstract: In one embodiment, a host processor includes a configuration circuit that, in response to identification of a first device capable of debugging a second device, is to configure a switch to enable device-to-device messaging between the first device and the second device, the device-to-device messaging comprising at least one of debug messaging or test messaging to be communicated without host processor involvement. Other embodiments are described and claimed.

Abstract: A Universal Serial Bus 4 (USB4) host system for tunneling USB2 data includes a USB controller and a first routing circuit communicatively coupled to the USB controller. The first routing circuit is to configure a downstream tunneled path between the USB controller and a second routing circuit. The first routing circuit is further to packetize outgoing USB2 data received from the USB controller into a first plurality of USB4 tunneled packets. The first routing circuit is further to encode the first plurality of USB4 tunneled packets for transmission to the second routing circuit via the downstream tunneled path, to initiate processing of the outgoing USB2 data by a USB2 device associated with the second routing circuit.

Abstract: A USB4 host system for offloading compute processing includes a host processor and a first routing circuit communicatively coupled to the host processor via an interface adapter. The first routing circuit is to decode device capability information received via a USB Type-C communication link from a second routing circuit. The device capability information indicates the second routing circuit is configured for offload processing. A downstream tunneled path is configured between the host processor and the second routing circuit based on the device capability information. The downstream tunneled path includes the USB Type-C communication link. One or more acceleration commands and operands/data from the host processor are packetized into a first plurality of USB4 tunneled packets. The first plurality of USB4 tunneled packets is encoded for transmission to the second routing circuit via the downstream tunneled path, to initiate the offload processing of the operands/data by the second routing circuit.

Abstract: Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed example apparatus also control a device layer of the audio stack to enter a device layer low power mode in response to a first determination that the audio latency requirement(s) is/are met by the audio latency characteristic(s). Disclosed example apparatus further control a hardware layer of the audio stack to enter a hardware layer low power mode in response to the first determination and a second determination that an operation condition for entry into the hardware layer low power mode is met.

Abstract: In one embodiment, an apparatus includes: a converter to receive and convert single-ended data to differential data, and receive and convert a single-ended clock signal to a differential clock signal; a multiplexer coupled to the converter to receive the differential data and the differential clock signal; and a controller coupled to the multiplexer. In response to an indication that a device coupled to the apparatus is capable of an alternate mode, the controller is to configure the multiplexer to send the differential data on at least one of a plurality of differential pairs of data lanes. Other embodiments are described and claimed.