Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: perform a route lookup for a packet based on first and second lookup operations, wherein the first lookup operation comprises a longest prefix match (LPM) to output a route identifier based on a destination Internet Protocol (IP) address of the packet and wherein the second look up operation comprises an exact match operation to determine an action based on the route identifier and a packet header.

Abstract: Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.

Abstract: Examples described herein relate to a packet processing device. In some examples, the packet processing device includes multiple processors and data plane circuitry. In some examples, a first processor of the multiple processors is to perform a first control plane, a second processor of the multiple processors is to perform a second control plane, and the first and second control planes are to communicate through an interface and wherein the first control plane is to discover capabilities of data plane circuitry and configure operation of the data plane circuitry by the interface.

Abstract: Examples described herein relate to a packet processing device that includes circuitry to perform packet processing operations according to a configuration and circuitry to execute control plane software to provide the configuration to the circuitry to perform packet processing operations according to the configuration. In some examples, the circuitry to perform packet processing operations according to the configuration is to continue operation independent of operation of the circuitry to execute control plane software.

Abstract: A data exchange adaptor that synchronizes data between an enterprise system operated by a company and a cloud-based system operated by a third party other than the company. The data exchange adaptor enables exchange of data between the enterprise system and the cloud-based system and controls storage and retrieval of data at the enterprise system and the cloud-based system. The data exchange adaptor also performs transport level security for communications that exchange data between the enterprise system and the cloud-based system and access level security for data stored to the enterprise system and the cloud-based system. The data exchange adaptor further schedules synchronization of data between the enterprise system and the cloud-based system and allows the enterprise system to retain control over the synchronization of data between the enterprise system and the cloud-based system.

Abstract: A data exchange adaptor that synchronizes data between an enterprise system operated by a company and a cloud-based system operated by a third party other than the company. The data exchange adaptor enables exchange of data between the enterprise system and the cloud-based system and controls storage and retrieval of data at the enterprise system and the cloud-based system. The data exchange adaptor also performs transport level security for communications that exchange data between the enterprise system and the cloud-based system and access level security for data stored to the enterprise system and the cloud-based system. The data exchange adaptor further schedules synchronization of data between the enterprise system and the cloud-based system and allows the enterprise system to retain control over the synchronization of data between the enterprise system and the cloud-based system.

Abstract: A method of circuit synthesis which considers all circuit configurations that can be designed utilizing a retiming with logic duplication (RLD) methodology. These circuit configurations (RLD configurations) each have significantly different area, performance and testability characteristics and are represented as a set of feasible solutions to an integer linear program (ILP). The ILP permits the evaluation of different design and testability metrics for each of the configurations. An approach to solve several useful special cases of the ILP in polynomial time and an application of RLD transformation to partial scan is shown. Using this method, a desired RLD configuration is produced having a minimal number of duplicated logic nodes.

Abstract: In partial scan testing of a circuit the optimal quantity of scan flip-flops required to eliminate all feedback, except self-loops, in a circuit is determined. For determining a minimal feedback vertex set (MFVS) for the S-graph of a circuit to be tested, MFVS-preserving transformations, partitioned search strategy and integer linear program (ILP)-based lower bounding techniques are combined to obtain an exact algorithm for computing the MFVS. The result is used in the fabrication of the circuit with minimal overhead in terms of area and performance degradation as a result of providing the capability to perform partial scan testing of the fabricated circuit.