Abstract: The system may speed up reduced instruction set computing/single instruction, multiple data (RISCV/SIMD) vector processing (VP) by adding a register circuit for an additional vector register file for a total of two VRF registers. One of the VRF registers may be used for data transfers to and from memory, and the other VRF register may be used for arithmetic logic unit (ALU) operands. The VRFs may be switched alternatively to perform the data transfers and operands.

Abstract: A circuit, and method for using same comprising, a first intermediate memory communicatively coupled with a vector processor and a RAM, wherein the vector processor is communicatively coupled with the RAM, an address sequence memory to store non-linear RAM addresses corresponding to linear locations in the first intermediate memory, a data sequencer to read a first frame of data from the RAM to the first intermediate memory based on addresses stored in the address sequence memory, and the first intermediate memory to provide a linearized frame of data to the vector processor to execute a vector instruction