Patents by Inventor Arup Bhattacharyya
Arup Bhattacharyya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11264472Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.Type: GrantFiled: July 23, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 11211503Abstract: In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.Type: GrantFiled: July 26, 2019Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 11211124Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.Type: GrantFiled: March 18, 2021Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 11087842Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.Type: GrantFiled: August 9, 2019Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Publication number: 20210225446Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.Type: ApplicationFiled: March 18, 2021Publication date: July 22, 2021Inventor: Arup Bhattacharyya
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Patent number: 11031283Abstract: The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. A material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.Type: GrantFiled: November 6, 2019Date of Patent: June 8, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10998042Abstract: An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.Type: GrantFiled: August 13, 2019Date of Patent: May 4, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10957389Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.Type: GrantFiled: January 16, 2020Date of Patent: March 23, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10892340Abstract: In an example, a memory cell may have an interface dielectric adjacent to a semiconductor, a tunnel dielectric adjacent to the interface dielectric, a charge trap adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge trap, and a control gate adjacent to the blocking dielectric.Type: GrantFiled: March 5, 2019Date of Patent: January 12, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Publication number: 20200357890Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Inventor: Arup Bhattacharyya
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Patent number: 10811424Abstract: The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.Type: GrantFiled: August 26, 2019Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10797053Abstract: Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.Type: GrantFiled: April 18, 2019Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10741658Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.Type: GrantFiled: September 17, 2018Date of Patent: August 11, 2020Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Publication number: 20200152269Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Inventor: Arup Bhattacharyya
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Publication number: 20200075394Abstract: The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. A material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventor: Arup Bhattacharyya
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Patent number: 10566053Abstract: Memory cells programmed via multi-mechanism charge transports are described herein. An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.Type: GrantFiled: September 21, 2018Date of Patent: February 18, 2020Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10546639Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.Type: GrantFiled: September 18, 2018Date of Patent: January 28, 2020Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10541027Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.Type: GrantFiled: December 12, 2018Date of Patent: January 21, 2020Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Publication number: 20190386017Abstract: The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.Type: ApplicationFiled: August 26, 2019Publication date: December 19, 2019Inventor: Arup Bhattacharyya
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Publication number: 20190371401Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.Type: ApplicationFiled: August 9, 2019Publication date: December 5, 2019Inventor: Arup Bhattacharyya