Patents by Inventor Arup Kocheethra GEORGE

Arup Kocheethra GEORGE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reconfigurable digital converter for converting sensing signal of plurality of sensors into digital value
    Patent number: 10892766
    Abstract: A digital converter and a controlling method are disclosed. The digital converter includes a sensing oscillator including a plurality of tri-state buffers configured to generate a sensing clock period signal corresponding to a change value of at least one of a resistive sensor and a capacitive sensor, a reference oscillator configured to generate a predetermined fixed clock period signal, a processor configured to change a connection state of the plurality of tri-state buffers, a frequency divider configured to scale up the generated sensing clock period signal based on a predetermined value; and a counter configured to count the scaled up sensing clock period signal based on the generated fixed clock cycle signal and output a counted digital value.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 12, 2021
    Assignee: DAEGU GYEONGBUK INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jung Hyup Lee, Arup Kocheethra George, Wooyoon Shim
  • RECONFIGURABLE DIGITAL CONVERTER FOR CONVERTING SENSING SIGNAL OF PLURALITY OF SENSORS INTO DIGITAL VALUE
    Publication number: 20190348990
    Abstract: A digital converter and a controlling method are disclosed. The digital converter includes a sensing oscillator including a plurality of tri-state buffers configured to generate a sensing clock period signal corresponding to a change value of at least one of a resistive sensor and a capacitive sensor, a reference oscillator configured to generate a predetermined fixed clock period signal, a processor configured to change a connection state of the plurality of tri-state buffers, a frequency divider configured to scale up the generated sensing clock period signal based on a predetermined value; and a counter configured to count the scaled up sensing clock period signal based on the generated fixed clock cycle signal and output a counted digital value.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 14, 2019
    Applicant: Daegu Gyeongbuk Institute of Science and Technology
    Inventors: Jung Hyup LEE, Arup Kocheethra GEORGE, Wooyoon SHIM