Patents by Inventor Arup Mukherji

Arup Mukherji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240022268
    Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 18, 2024
    Inventors: Euisoo Yoo, Arup Mukherji, Rangakrishnan Srinivasan, Vitor Pereira, Zhongda Wang, Sriharsha Vasadi
  • Patent number: 11804862
    Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 31, 2023
    Assignee: Silicon Laboratories Inc.
    Inventors: Euisoo Yoo, Arup Mukherji, Rangakrishnan Srinivasan, Vitor Pereira, Zhongda Wang, Sriharsha Vasadi
  • Publication number: 20230099832
    Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Euisoo Yoo, Arup Mukherji, Rangakrishnan Srinivasan, Vitor Pereira, Zhongda Wang, Sriharsha Vasadi
  • Publication number: 20220318046
    Abstract: A system, security domain and method for providing a security execution environment for security-relevant, domain-specific applications in a virtualized system.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Inventors: Balakrishnan Paulraj, Achim Schaefer, Arup Mukherji
  • Patent number: 11387857
    Abstract: A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: July 12, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Arup Mukherji, Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Publication number: 20210175917
    Abstract: A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.
    Type: Application
    Filed: August 20, 2020
    Publication date: June 10, 2021
    Inventors: Arup Mukherji, Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Patent number: 10969416
    Abstract: An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 6, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Vitor Pereira, Arup Mukherji
  • Patent number: 10972077
    Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 6, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Steffen Skaug, Vitor Pereira, Arup Mukherji
  • Publication number: 20200328731
    Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Steffen Skaug, Vitor Pereira, Arup Mukherji
  • Publication number: 20200191849
    Abstract: An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: VITOR PEREIRA, ARUP MUKHERJI
  • Patent number: 10181868
    Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes a single-balanced passive mixer driven by the output of a low noise amplifier (LNA) and a passive filter driven by an output of the single-balanced passive mixer. The RF receiver further includes a programmable gain amplifier (PGA) having an input resistance that generates noise, where the PGA is driven by an output of the passive filter, and the noise generated by the input resistance of the PGA is suppressed.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 15, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Navin Harwalkar, Arup Mukherji, John M. Khoury
  • Publication number: 20180351593
    Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes a single-balanced passive mixer driven by the output of a low noise amplifier (LNA) and a passive filter driven by an output of the single-balanced passive mixer. The RF receiver further includes a programmable gain amplifier (PGA) having an input resistance that generates noise, where the PGA is driven by an output of the passive filter, and the noise generated by the input resistance of the PGA is suppressed.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Navin Harwalkar, Arup Mukherji, John M. Khoury
  • Patent number: 10141971
    Abstract: Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 27, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Mohamed Elkholy, Ayman Shafik, Yang Gao, Arup Mukherji, Navin Harwalkar
  • Patent number: 9966900
    Abstract: An apparatus includes a first oscillator to generate an output signal that has a first frequency. The apparatus further includes a second oscillator to generate an output signal that has a second frequency. The second frequency varies as a function of temperature. The apparatus further includes a controller that counts a number of cycles of the output signal of the second oscillator in order to determine whether to calibrate the first oscillator.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 8, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Marty Pflum, Arup Mukherji, John M. Khoury
  • Publication number: 20180054162
    Abstract: An apparatus includes a first oscillator to generate an output signal that has a first frequency. The apparatus further includes a second oscillator to generate an output signal that has a second frequency. The second frequency varies as a function of temperature. The apparatus further includes a controller that counts a number of cycles of the output signal of the second oscillator in order to determine whether to calibrate the first oscillator.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 22, 2018
    Inventors: Marty Pflum, Arup Mukherji, John M. Khoury
  • Patent number: 9823687
    Abstract: A technique includes using a first oscillator to clock operations of a radio of an integrated circuit (IC). The technique includes intermittently using the first oscillator to frequency tune a second oscillator of the IC.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 21, 2017
    Assignee: SILICON LABORATORIES INC.
    Inventors: Arup Mukherji, John M. Khoury
  • Patent number: 9757481
    Abstract: UV-Laser-synthesized, fluorescent, spherical and magnetic nanoparticles are loaded Sophorolipid mesostructures useful for bio-imaging and therapeutic applications.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 12, 2017
    Assignee: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Asmita Ashutosh Prabhune, Pradeep Kumar Singh, Ruchira Arup Mukherji, Satishchandra Balkrishna Ogale
  • Publication number: 20170177020
    Abstract: A technique includes using a first oscillator to clock operations of a radio of an integrated circuit (IC). The technique includes intermittently using the first oscillator to frequency tune a second oscillator of the IC.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: ARUP MUKHERJI, JOHN M. KHOURY
  • Publication number: 20150159180
    Abstract: The inventors disclose a novel room temperature process for the synthesis of crystalline xylitol with high yield and purity from D-xylose using Pichia caribbica yeasts that acts as a quorum sensing antagonist that prevents bio film formation by gram-negative bacteria. Further a mild and safe procedure for xylitol extraction is disclosed.
    Type: Application
    Filed: July 16, 2013
    Publication date: June 11, 2015
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Asmita Ashutosh Prabhune, Kasturi Laxman, Ruchira Arup Mukherji
  • Publication number: 20150139910
    Abstract: UV-Laser-synthesized, fluorescent, spherical and magnetic nanoparticles are loaded Sophorolipid mesostructures useful for bio-imaging and therapeutic applications.
    Type: Application
    Filed: April 30, 2013
    Publication date: May 21, 2015
    Inventors: Asmita Ashutosh Prabhune, Pradeep Kumar Singh, Ruchira Arup Mukherji, Satishchandra Balkrishna Ogale