Patents by Inventor Arvid G. Sammuli

Arvid G. Sammuli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8379403
    Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: February 19, 2013
    Assignee: QUALCOMM, Incorporated
    Inventors: David W. Waite, James L. Blair, Ashish Lohiya, Arvid G. Sammuli, Jeffrey T. Smith, Saritha Narra
  • Patent number: 7932736
    Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: April 26, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Srinivas Varadarajan, Michael Laisne, Raghunath R. Bhattagiri, Arvid G. Sammuli
  • Publication number: 20100255690
    Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 7, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: David W. Waite, James L. Blair, Ashish Lohiya, Arvid G. Sammuli, Jeffrey T. Smith, Saritha Narra
  • Publication number: 20100244871
    Abstract: Space transformer connectors for coupling printed circuit boards and/or other electrical connections are disclosed. A scalar design of a multilayer space transformer connector allows for a variety of pad-array field connections. A conductive elastomer interface provides for repeated and consistent coupling and decoupling of the space transformer connector.
    Type: Application
    Filed: February 22, 2010
    Publication date: September 30, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: James L. Blair, David W. Waite, Ashish Lohiya, Saritha Narra, Jeffrey T. Smith, Arvid G. Sammuli
  • Patent number: 7750660
    Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: July 6, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Srinivas Varadarajan, Michael Laisne, Raghunath R. Bhattagiri, Arvid G. Sammuli
  • Publication number: 20100141286
    Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Srinivas Varadarajan, Michael Laisne, Raghunath R. Bhattagiri, Arvid G. Sammuli