Abstract: An electronic module including a logical interlock for interconnecting two data sources to a modem whereby only one of the two data sources is allowed to transmit data at a time. First and second flip-flops and logic gates controlled thereby are provided such that the first data source to present a Request-to-Send (RTS) signal is awarded priority and thereby selected to receive a Clear-to-Send (CTS) signal from the modem. A subsequent RTS signal from the non-selected data source is ineffective in establishing communication with such non-selected data source since that source is blocked from receiving a CTS signal from the modem. A clock signal is effectively employed to ensure that simultaneously-generated RTS signals from the two data sources are only responded to by one of the two data sources.