Patents by Inventor Arvind Bomdica
Arvind Bomdica has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7999595Abstract: A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.Type: GrantFiled: September 16, 2009Date of Patent: August 16, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Jinyung Namkoong, Arvind Bomdica, Ming-Ju Lee
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Publication number: 20110148838Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Kevin Yikai Liang, Xin Liu, Arvind Bomdica, Ming-Ju Edward Lee
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Publication number: 20110133788Abstract: A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.Type: ApplicationFiled: December 8, 2009Publication date: June 9, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Xin Liu, Arvind Bomdica, Yikai Liang, Ming-Ju Edward Lee, Rohit Rathi, Jinyung Namkoong
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Publication number: 20110063010Abstract: A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.Type: ApplicationFiled: September 16, 2009Publication date: March 17, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Jinyung Namkoong, Arvind Bomdica, Ming-Ju Lee
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Publication number: 20100238599Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
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Publication number: 20100238598Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
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Patent number: 7714615Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.Type: GrantFiled: February 18, 2008Date of Patent: May 11, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Yikai Liang, Arvind Bomdica, Min Xu, Ming-Ju Lee
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Patent number: 7710150Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: GrantFiled: March 12, 2008Date of Patent: May 4, 2010Assignee: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang
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Patent number: 7688925Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.Type: GrantFiled: August 1, 2005Date of Patent: March 30, 2010Assignee: ATI Technologies, Inc.Inventors: Edward Lee, Arvind Bomdica, Lin Chen, Claude Gauthier, Sam Huynh, Hiok-Tiaq Ng, John Ling, Jennifer Ho, Siji Menokki Kandiyil, Gin Yee, Joseph Macri
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Patent number: 7659768Abstract: A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.Type: GrantFiled: December 19, 2008Date of Patent: February 9, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Samu Suryanarayana, Arvind Bomdica, Yikai Liang
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Publication number: 20090167405Abstract: A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Samu Suryanarayana, Arvind Bomdica, Yikai Liang
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Publication number: 20090168854Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.Type: ApplicationFiled: February 18, 2008Publication date: July 2, 2009Applicant: Advanced Micro DevicesInventors: Yikai Liang, Arvind Bomdica, Min Xu, Ming-Ju Ml. Lee
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Patent number: 7522010Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.Type: GrantFiled: April 30, 2007Date of Patent: April 21, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Kevin YiKai Liang, Arvind Bomdica, Min Xu, Ming So
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Publication number: 20080284468Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.Type: ApplicationFiled: May 15, 2007Publication date: November 20, 2008Inventors: Oleg Drapkin, Grigori Temkine, Marcus Ng, Kevin Yikai Liang, Arvind Bomdica, Siji Menokki Kandiyil, Ming So, Samu Suryanarayana
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Publication number: 20080266009Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Inventors: Kevin YiKai Liang, Arvind Bomdica, Min Xu, Ming So
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Publication number: 20080157817Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: ApplicationFiled: March 12, 2008Publication date: July 3, 2008Applicant: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang
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Patent number: 7345510Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: GrantFiled: August 31, 2006Date of Patent: March 18, 2008Assignee: ATI Technologies Inc.Inventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang
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Publication number: 20080054942Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: ATI Technologies Inc.Inventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang
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Publication number: 20070036020Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.Type: ApplicationFiled: August 1, 2005Publication date: February 15, 2007Inventors: Edward Lee, Arvind Bomdica, Lin Chen, Claude Gauthier, Sam Huynh, Hiok-Tiaq Ng, John Ling, Jennifer Ho, Siji M.K., Gin Yee, Joseph Macri