Abstract: Indeterministic launch of test transactions in a system-on-chip device having asynchronous paths may be avoided by gating test mode bus transactions at the functional (IP) module interface. The gated bus transactions are released using an external trigger in order to control loss of cycle accuracy caused by on-board synchronizers during functional testing. Conventional interfaces can be driven from automatic test equipment and controlled in order to account for PVT variations and achieve deterministic and stable behavior of the device while being tested.

Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.

Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.

Abstract: An electronic design automation (EDA) tool that analyzes a circuit design to identify sequential elements (flip-flops) that do not need to be reset, for example, because they do not need to be initialized in order to be in a known state, and converts the identified sequential elements to non-resettable circuits, which saves power and area.

Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.

Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.

Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.

Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.