Abstract: Method and apparatus for automated test generation are provided. One or more coverage events are received. One or more test components involved in triggering each of one or more coverage events are recorded. The one or more test components are stored in a database, each test component being linked to a corresponding coverage event. A dependency graph is generated, representing relationships between the one or more test components for the one or more coverage events. A correlation between each test component and the corresponding coverage event is determined by performing correlation analysis. A ranking list for each of one or more coverage events is generated, where the ranking list comprises the one or more test components involved in triggering the corresponding coverage event, and the one or more test components are ranked based on the determined correlation.

Abstract: An approach for optimizing error-checking logic in a processor design is disclosed. The approach includes performing a static analysis on the processor design, wherein the processor design includes one or more latches and one or more checkers and generating a bipartite graph mapping between the one or more latches and the one or more checkers. The approach also determines checker set cover based on the mapping and preselecting timing critical checkers. The approach also determines redundant checkers based on checker activity and eliminate redundant checkers. Finally, the approach determines whether convergence criteria has been met.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: A method, computer program product, and a computer system are disclosed for providing a trace abstraction framework to compute trace-based functional coverage models that in one or more embodiments receive a set of traces; rewrite a trace of the set of traces into a second trace; abstract the second trace; rewrite the abstracted second trace; and generate an abstract trace representative the trace of the set of traces.

Abstract: A method, computer program product, and a computer system are disclosed for providing a trace abstraction framework to compute trace-based functional coverage models that in one or more embodiments receive a set of traces; rewrite a trace of the set of traces into a second trace; abstract the second trace; rewrite the abstracted second trace; and generate an abstract trace representative the trace of the set of traces.