Patents by Inventor Arvind Haran

Arvind Haran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Error protection analysis of an integrated circuit
    Patent number: 12188979
    Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: January 7, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin Neil Trombley, Chung-Lung K. Shum, Karl Evan Smock Anderson, Bodo Hoppe, Erica Stuecheli, Shiri Moran, Patrick James Meaney, Arvind Haran, Douglas Balazich
  • ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT
    Publication number: 20240402246
    Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: BENJAMIN NEIL TROMBLEY, CHUNG-LUNG K. SHUM, KARL EVAN SMOCK ANDERSON, BODO HOPPE, ERICA STUECHELI, SHIRI MORAN, PATRICK JAMES MEANEY, ARVIND HARAN, DOUGLAS BALAZICH
  • Trace-based generation of states within a system
    Patent number: 11481534
    Abstract: A method, computer program product, and a computer system are disclosed for providing a trace abstraction framework to compute trace-based functional coverage models that in one or more embodiments receive a set of traces; rewrite a trace of the set of traces into a second trace; abstract the second trace; rewrite the abstracted second trace; and generate an abstract trace representative the trace of the set of traces.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Flavio M. De Paula, Bradley D. Bingham, Arvind Haran
  • TRACE-BASED GENERATION OF STATES WITHIN A SYSTEM
    Publication number: 20200285712
    Abstract: A method, computer program product, and a computer system are disclosed for providing a trace abstraction framework to compute trace-based functional coverage models that in one or more embodiments receive a set of traces; rewrite a trace of the set of traces into a second trace; abstract the second trace; rewrite the abstracted second trace; and generate an abstract trace representative the trace of the set of traces.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Flavio M. De Paula, Bradley D. Bingham, Arvind Haran