Abstract: This disclosure provides methods, devices and systems for reducing power consumption when a station (STA) is operating in a listen mode. In some aspects, to reduce power consumption in the listen mode, the STA may alternate between monitoring a wireless channel for packets and not monitoring the wireless channel. When the STA is monitoring the wireless channel for packets in the listen mode, the STA may configure packet detection components to a power-on state. When the STA is not monitoring the wireless channel in the listen mode, the STA may configure packet detection components to a power-off state. During the power-on state of the listen mode, the STA may detect a preamble of a packet that was transmitted over the wireless channel. In response to detecting the preamble of the packet, the STA may switch from the listen mode to a receive mode to process the packet.

Abstract: This disclosure provides methods, devices and systems for reducing power consumption when a station (STA) is operating in a listen mode. In some aspects, to reduce power consumption in the listen mode, the STA may alternate between monitoring a wireless channel for packets and not monitoring the wireless channel. When the STA is monitoring the wireless channel for packets in the listen mode, the STA may configure packet detection components to a power-on state. When the STA is not monitoring the wireless channel in the listen mode, the STA may configure packet detection components to a power-off state. During the power-on state of the listen mode, the STA may detect a preamble of a packet that was transmitted over the wireless channel. In response to detecting the preamble of the packet, the STA may switch from the listen mode to a receive mode to process the packet.

Abstract: This disclosure provides methods, devices and systems for reducing power consumption when a station (STA) is operating in a listen mode. In some aspects, to reduce power consumption in the listen mode, the STA may alternate between monitoring a wireless channel for packets and not monitoring the wireless channel. When the STA is monitoring the wireless channel for packets in the listen mode, the STA may configure packet detection components to a power-on state. When the STA is not monitoring the wireless channel in the listen mode, the STA may configure packet detection components to a power-off state. During the power-on state of the listen mode, the STA may detect a preamble of a packet that was transmitted over the wireless channel. In response to detecting the preamble of the packet, the STA may switch from the listen mode to a receive mode to process the packet.

Abstract: This disclosure provides systems and apparatuses for reducing flicker noise in output signals provided by a radio frequency (RF) amplifier. In some implementations, the RF amplifier may include a bias generator to provide one or more bias signals to control operating points of devices and circuits of the RF amplifier. The bias generator may include a feedback circuit to generate a current to attenuate flicker noise within the bias generator. In some implementations, the feedback circuit may receive a bias voltage and may generate the current based on a frequency of the bias voltage.

Abstract: This disclosure provides systems and apparatuses for reducing flicker noise in output signals provided by a radio frequency (RF) amplifier. In some implementations, the RF amplifier may include a bias generator to provide one or more bias signals to control operating points of devices and circuits of the RF amplifier. The bias generator may include a feedback circuit to generate a current to attenuate flicker noise within the bias generator. In some implementations, the feedback circuit may receive a bias voltage and may generate the current based on a frequency of the bias voltage.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

Abstract: A multipath circuit is described that has multiple signal paths and various common components used for normal operation. Each of the multiple signal paths also has multiple circuit blocks defining the functionality of the signal path. A shared access path is provided through the third winding of a three-way transformer for each signal path. Multiple switches are provided in the multipath circuit that couple to the third winding in each of the multiple signal paths. The switches are also coupled to the various common components. Selected ones of these switches may be closed to provide a shared access path between a common component and one of the signal paths or between a common components and one of the circuit blocks in one of the signal paths.

Abstract: A multipath circuit is described that has multiple signal paths and various common components used for normal operation. Each of the multiple signal paths also has multiple circuit blocks defining the functionality of the signal path. A shared access path is provided through the third winding of a three-way transformer for each signal path. Multiple switches are provided in the multipath circuit that couple to the third winding in each of the multiple signal paths. The switches are also coupled to the various common components. Selected ones of these switches may be closed to provide a shared access path between a common component and one of the signal paths or between a common components and one of the circuit blocks in one of the signal paths.

Abstract: A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC.

Abstract: Techniques for biasing an amplifier using a replica circuit are disclosed. In an embodiment, a replica circuit having substantially the same topology and sizing as a push-pull amplifier circuit is coupled to a main push-pull amplifier circuit. A transistor in the replica circuit may be biased using feedback to generate a predetermined DC output voltage level, and such bias level may be applied to a corresponding transistor in the main push-pull amplifier circuit. In another embodiment, a transistor in a current bias module may be used to bias corresponding transistors in the main push-pull amplifier circuit and the replica circuit. Further techniques are disclosed for configuring the amplifier to have a non-uniform step size with finer resolution at lower power levels and coarser resolution at higher power levels to reduce power consumption at lower power levels.

Abstract: A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC.

Abstract: Techniques for biasing an amplifier using a replica circuit are disclosed. In an embodiment, a replica circuit having substantially the same topology and sizing as a push-pull amplifier circuit is coupled to a main push-pull amplifier circuit. A transistor in the replica circuit may be biased using feedback to generate a predetermined DC output voltage level, and such bias level may be applied to a corresponding transistor in the main push-pull amplifier circuit. In another embodiment, a transistor in a current bias module may be used to bias corresponding transistors in the main push-pull amplifier circuit and the replica circuit. Further techniques are disclosed for configuring the amplifier to have a non-uniform step size with finer resolution at lower power levels and coarser resolution at higher power levels to reduce power consumption at lower power levels.