Patents by Inventor Arvind Krishnaswamy
Arvind Krishnaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240403411Abstract: Various embodiments include methods and devices for maintaining control flow integrity in computing devices. Embodiments may include identifying indirect function call candidate functions from a source code by a compiler, replacing, by the compiler, an indirect function call from the source code with a call to a wrapper function, and collocating the indirect function call candidate functions in at least one range of addresses of memory by a linker. The wrapper function may be configured to determine whether an address to be passed to the indirect function call is within the at least one range of addresses of memory.Type: ApplicationFiled: November 17, 2022Publication date: December 5, 2024Inventors: Sundeep KUSHWAHA, Arvind KRISHNASWAMY, Sergei LARIN, Can ACAR, Tianshuo SU, Awanish PANDEY, Richard SENIOR
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Patent number: 11599625Abstract: Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.Type: GrantFiled: January 28, 2021Date of Patent: March 7, 2023Assignee: QUALCOMM IncorporatedInventors: Arvind Krishnaswamy, Suresh Kumar Venkumahanti, Charles Tabony
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Publication number: 20220237283Abstract: Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.Type: ApplicationFiled: January 28, 2021Publication date: July 28, 2022Inventors: Arvind KRISHNASWAMY, Suresh Kumar VENKUMAHANTI, Charles TABONY
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Patent number: 11386012Abstract: Various embodiments include methods and devices for generating a memory map configured to map virtual addresses of pages to physical addresses, in which pages of a same size are grouped into regions. The embodiments may include adding a first entry for a first additional page to a first region in the memory map, shifting virtual addresses of the first region to accommodate a shift of virtual addresses of the first region allocated for code by a sub-page granular shift amount, mapping shifted virtual addresses of the first entry for the first additional page to physical address mapped to a first lowest shifted virtually addressed page of the first region, and shifting the virtual addresses of the first region allocated for code by a sub-page granular shift amount, in which the virtual addresses of the first region allocated for code partially shift into the first entry for the first additional page.Type: GrantFiled: March 15, 2021Date of Patent: July 12, 2022Assignee: QUALCOMM IncorporatedInventors: Arvind Krishnaswamy, Richard Senior, Sundeep Kushwaha, Can Acar
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Publication number: 20200020330Abstract: Techniques for operating a voice-activated computing device are provided. These techniques can be used to prevent voice-based attacks on such devices. An example method according to these techniques includes receiving audio content comprising a voice command, monitoring electromagnetic (EM) emissions using an EM detector of the voice-activated computing device, determining whether the audio content comprising the voice command was generated electronically or was issued by a human user based on the EM emissions detected while receiving the audio content comprising the voice command, and preventing the voice command from being executed by the voice-activated computing device responsive to determining that the voice command was generated electronically.Type: ApplicationFiled: July 16, 2018Publication date: January 16, 2020Inventors: Xu GUO, Arvind KRISHNASWAMY, Liang CAI, Nabanita SEN, Jyotsna KRISHNASWAMY, Kenneth CHEN
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Patent number: 10114643Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.Type: GrantFiled: May 23, 2013Date of Patent: October 30, 2018Assignee: INTEL CORPORATIONInventors: Koichi Yamada, Palanivelra Shanmugavelayutham, Arvind Krishnaswamy, Jason M. Agron, Jiwei Lu
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Patent number: 10061609Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.Type: GrantFiled: October 31, 2016Date of Patent: August 28, 2018Assignee: Intel CorporationInventors: Arvind Krishnaswamy, Daniel M. Lavery
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Patent number: 10055585Abstract: Technologies for assembling an execution profile of an event are disclosed. The technologies may include monitoring the event for a branch instruction, generating a callback to a security module upon execution of the branch instruction, filtering the callback according to a plurality of event identifiers, and validating a code segment associated with the branch instruction, the code segment including code executed before the branch instruction and code executed after the branch instruction.Type: GrantFiled: August 28, 2013Date of Patent: August 21, 2018Assignee: McAfee, LLCInventors: Greg William Dalcher, Ravi L. Sahita, Palanivelra Shanmugavelayutham, Koichi Yamada, Arvind Krishnaswamy
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Patent number: 9880842Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.Type: GrantFiled: March 15, 2013Date of Patent: January 30, 2018Assignee: Intel CorporationInventors: Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy, David J. Sager, Jason M. Agron
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Patent number: 9672351Abstract: A method of producing a control stack includes: writing a plurality of control information entries into a control stack buffer that is internal to a processor in response to one or more function calls; and in response to the control stack buffer being full and receiving a further function call, writing: the plurality of control information entries to an external memory that is external to the processor; and a further control information entry, corresponding to the further function call, to the control stack buffer.Type: GrantFiled: February 2, 2015Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Arvind Krishnaswamy, Can Acar, Robert Turner
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Publication number: 20170046165Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Inventors: Arvind Krishnaswamy, Daniel M. Lavery
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Patent number: 9514305Abstract: Techniques for enforcing flow control of a software program in a processor are provided. An example method according to these techniques includes analyzing program code of the software program to identify a code pointer in the program code, generating an authentication tag based on the code pointer, and modifying the code pointer in the program code with the authentication tag to generate a tagged code pointer.Type: GrantFiled: October 17, 2014Date of Patent: December 6, 2016Assignee: QUALCOMM IncorporatedInventors: Can Acar, Arvind Krishnaswamy, Robert Turner
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Patent number: 9483275Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.Type: GrantFiled: December 16, 2011Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Arvind Krishnaswamy, Daniel M Lavery
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Publication number: 20160224784Abstract: A method of producing a control stack includes: writing a plurality of control information entries into a control stack buffer that is internal to a processor in response to one or more function calls; and in response to the control stack buffer being full and receiving a further function call, writing: the plurality of control information entries to an external memory that is external to the processor; and a further control information entry, corresponding to the further function call, to the control stack buffer.Type: ApplicationFiled: February 2, 2015Publication date: August 4, 2016Inventors: Arvind KRISHNASWAMY, Can ACAR, Robert TURNER
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Publication number: 20160110545Abstract: Techniques for enforcing flow control of a software program in a processor are provided. An example method according to these techniques includes analyzing program code of the software program to identify a code pointer in the program code, generating an authentication tag based on the code pointer, and modifying the code pointer in the program code with the authentication tag to generate a tagged code pointer.Type: ApplicationFiled: October 17, 2014Publication date: April 21, 2016Inventors: Can ACAR, Arvind KRISHNASWAMY, Robert TURNER
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Patent number: 9189233Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.Type: GrantFiled: June 26, 2012Date of Patent: November 17, 2015Assignee: INTEL CORPORATIONInventors: Ruchira Sasanka, Abhinav Das, Jeffrey J. Cook, Jayaram Bobba, Arvind Krishnaswamy, David J. Sager, Suresh Srinivas
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Patent number: 9171688Abstract: Devices for use in cold-field emission and methods of forming the device are generally presented. In one example, a method may include providing a conductive base, dispersing carbon-filled acrylic onto the conductive base to form a conductive film, coupling a copper plate to a first side of the conductive film, and irradiating the conductive film. The method may further include dispersing carbon nanotubes (CNTs) on a second side of the conductive film to form a substantially uniform layer of CNTs, removing excess CNTs from the second side, and curing the conductive film. In one example, a device may include a polycarbonate base, a layer of carbon-filled acrylic on one side of the polycarbonate base and a layer of irradiated carbon-filled acrylic on the other, a copper plate coupled to the carbon-filled acrylic, and a substantially uniform layer of randomly aligned CNTs dispersed on the irradiated carbon-filled acrylic.Type: GrantFiled: April 14, 2011Date of Patent: October 27, 2015Assignee: Indian Institute of ScienceInventors: Sandeep Venkit Anand, Arvind Krishnaswamy, Debiprosad Roy Mahapatra
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Patent number: 9171159Abstract: In an embodiment, a processor includes a binary translation engine to receive a code segment, to generate a binary translation of the code segment, and to store the binary translation in a translation cache, where the binary translation includes at least one policy check routine to be executed during execution of the binary translation on behalf of a security agent. Other embodiments are described and claimed.Type: GrantFiled: February 28, 2013Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Palanivelrajan R. Shanmugavelayutham, Koichi Yamada, Ravi Sahita, Arvind Krishnaswamy
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Patent number: 9135435Abstract: This disclosure is directed to binary translator driven program state relocation. In general, a device may protect vulnerable program functions by setting them as non-executable. If an attempt is made to execute a protected program function, the program may trap to a binary translator in the device that may be configured to relocate program state from what has already been established (e.g., on a stack register). Program state may include resources (e.g., memory locations) used by the program during the course of execution. The binary translator may then translate the program into an executable form based on the relocated program state, and may be executed accordingly. Intruding code that attempts to overcome normal program execution and implement hostile operations (e.g., based the program state that is reflected in the stack register) will not function as intended since the relocated program state will cause unexpected results.Type: GrantFiled: February 13, 2013Date of Patent: September 15, 2015Assignee: Intel CorporationInventors: Ashish Venkat, Arvind Krishnaswamy, Koichi Yamada, Palanivelrajan Rajan Shanmugavelayutham
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Patent number: 9013092Abstract: Energy harvesting elements or membranes are provided that use a layer of electrodes with a mixture of carbon nanotubes (CNT). The energy harvesting device of this type can be used as in sensor-based system in which on application of a bending load, the energy harvesting device produces a voltage across the electrodes. The energy harvesting device may include an electrode coating including carbon nanotubes (CNT) substantially homogenously dispersed in epoxy resin system to form a CNT-epoxy electrode coating. The CNT-epoxy electrode can be realized by dispersing about 5% CNT (by weight) in an epoxy-resin system, followed by mixing the system to achieve a near-homogenous dispersion resulting in a CNT-epoxy mixture. The CNT-epoxy mixture can then be uniformly coated on surfaces of a polymer to form electrodes.Type: GrantFiled: November 22, 2010Date of Patent: April 21, 2015Assignee: Indian Institute of ScienceInventors: Debiprosad Roy Mahapatra, Arvind Krishnaswamy