Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: A hybrid power generation system is presented. The system includes a first power generation subsystem including a prime mover driving a generator including a rotor and a stator, one or more first conversion units coupled to at least one of the rotor and the stator, a first direct current (DC) link, and one or more second conversion units coupled to a corresponding one or more first conversion units via the first DC link. The system includes one or more second power generation subsystems coupled to the first power generation subsystem and one or more power conversion subunits including one or more first bridge circuits coupled to a corresponding one or more second bridge circuits via one or more transformers, where at least one of the one or more second power generation subsystems and the first power generation subsystem includes the one or more power conversion subunits.

Abstract: Systems and methods for multi-modal user device authentication are disclosed. An example electronic device includes a first sensor, a microphone, a first camera, and a confidence analyzer to authenticate a subject as the authorized user in response to a user presence detection analyzer detecting a presence of the subject and one or more of (a) an audio data analyzer detecting a voice of an authorized user or (b) an image data analyzer detecting a feature of the authorized user. The example electronic device includes a processor to cause the electronic device to move from a first power state to a second power state in response to the confidence analyzer authenticating the user as the authorized user. The electronic device is to consume a greater amount of power in the second power state than the first power state.

Abstract: The present disclosure relates to a surgical fastener applying apparatus for applying fasteners to body tissue. The apparatus includes a cartridge receiving half-section defining an elongated channel member configured to releasably receive a firing assembly and a single use loading unit. A lockout structure prevents insertion of the single use loading unit into the channel member after the firing assembly is mounted to the cartridge receiving half-section. Alternatively, the lockout structure prevents full insertion of the firing assembly into the cartridge receiving half-section, if the single use loading unit is not engaged with the firing assembly.

Abstract: An interposer is electrically connected to heterogenous IC chips. A first IC chip is electrically connected to a first IC chip facing surface of the interposer. One or more second IC chips are electrically connected to a carrier facing surface of the interposer. The interposer may be electrically connected to a carrier which includes one or more topographic features that provide clearance for a respective second IC chip. Power and/or ground potential may be provided by or though the carrier to the one or more second IC chips and to the first IC chip by way of the interposer. An access instruction to pass data to the second IC chip or to obtain data from the second IC chip may be provided by the first IC chip to the one or more second IC chips by way of the interposer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A blockchain test configuration may provide a simple and secure infrastructure for testing applications. One example method of operation may comprise one or more of transmitting a request to a network of nodes to test a test package associated with an application. The method may also include receiving results based on the test of the test package and recording the results in a blockchain.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

Abstract: A method and associated system for operating a power generation to supply real and reactive power to a grid includes determining a total reactive power demand made on the system during a first, stable grid state. A first reactive power portion of the reactive power demand is supplied by a generator, and a second reactive power portion is supplied by a reactive power compensation device, wherein the second reactive power portion may be greater than the first reactive power portion. Upon detection of a grid fault, the first reactive power portion is increased and the second reactive power portion is decreased.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: A power generation system (100, 200, 300, 400) is presented. The power generation system includes a prime mover (102), a doubly-fed induction generator (DFIG) (104) having a rotor winding (126) and a stator winding (122), a rotor-side converter (106), a line-side converter (108), and a secondary power source (110, 401) electrically coupled to a DC-link (128). Additionally, the power generation system includes a control sub-system (112, 212, 312) having a controller, and a plurality of switching elements (130, and 132 or 201). The controller is configured to selectively control switching of one or more switching elements (130, and 132 or 201) based on a value of an operating parameter corresponding to at least one of the prime mover, the DFIG, or the secondary power source to connect the rotor-side converter in parallel to the line-side converter to increase an electrical power production by the power generation system.

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

Abstract: The present application relates to a method for controlling a power system connected to a power grid, including: receiving a reactive power instruction and a measured reactive power from a generator; generating a reactive power error signal based on the difference between the reactive power instruction and the measured reactive power; receiving the reactive power error signal; generating a voltage instruction based on reactive power error signal; generating a voltage droop signal based on a reference reactance and a voltage at a point of common coupling; generating a voltage error signal according to at least one of the voltage instruction or the measured terminal voltage of the generator and the voltage droop signal; and producing a reactive current instruction for the converter power path based on the voltage error signal. The present application also discloses a control system for a power system connected to a power grid and a wind farm.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A surgical fastener applying apparatus for applying fasteners to body tissue. The apparatus includes a clamping lever including a cantilevered locking member for engaging a catch member positioned at the proximal portion of a cartridge receiving half-section of the apparatus to retain the clamping lever in a clamped position. The clamping lever can include a protrusion which is receivable in a depression on the cartridge receiving half-section. The apparatus includes a disposable firing assembly and cartridge.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

Abstract: One embodiment provides a method, including: receiving at least two challenge test mechanisms of different challenge test modalities, wherein a challenge test mechanism comprises a challenge portion of a challenge-response test for distinguishing between a human operator and a computer; receiving challenge test operators for combining the at least two challenge test mechanisms; generating a composite challenge task by combining the at least two challenge test mechanisms using the identified challenge test operators; identifying any errors in the composite challenge task by running the composite challenge task; evaluating the composite challenge task to determine (i) a challenge difficulty for a human operator and (ii) a challenge difficulty for a computer; and implementing the composite challenge task if (i) no errors are identified at the composite challenge task analyzer, (ii) the challenge difficulty for a human operator is below a predetermined threshold, and (iii) the challenge difficulty for a computer

Abstract: Techniques for analyzing an execution of a query statement based on a random archive are disclosed. A plurality of query statements that are executed during a particular time period are identified. A random sampling function is executed to randomly select a set of query statements from the plurality of query statements. Execution plans and/or performance metrics associated with each execution of the randomly-selected query statements are stored into a random archive. Responsive to determining that a performance metric for a current execution of a particular query statement does not satisfy a performance criteria, information associated with the particular query statement from the random archive is analyzed. A model plan characteristic associated with an execution of the particular query statement stored in the random archive is determined. An execution plan associated with the model plan characteristic is determined for another execution of the particular query statement.