Patents by Inventor Arvind Sherigar
Arvind Sherigar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11323022Abstract: A system for controlling an inductor current of a boost converter includes a start-up controller that is configured to generate a control signal that has a fixed on-time duration and a dynamic off-time duration that decreases with each cycle of the control signal, and a pulse width modulation (PWM) circuit that is configured to generate a PWM signal. During a start-up of the boost converter, the PWM signal transitions from a deactivated state to an activated state when the control signal is activated, and from an activated state to a deactivated state when the inductor current is equal to a reference current. The reference current corresponds to a peak value of the inductor current during the start-up. Thus, during the start-up, the duty cycle of the PWM signal increases with each cycle of the PWM signal. The PWM signal is provided to the boost converter for controlling the inductor current.Type: GrantFiled: May 28, 2020Date of Patent: May 3, 2022Assignee: NXP B.V.Inventors: Arvind Sherigar, Samiran Dam, Ashutosh Ravindra Joharapurkar
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Publication number: 20210376725Abstract: A system for controlling an inductor current of a boost converter includes a start-up controller that is configured to generate a control signal that has a fixed on-time duration and a dynamic off-time duration that decreases with each cycle of the control signal, and a pulse width modulation (PWM) circuit that is configured to generate a PWM signal. During a start-up of the boost converter, the PWM signal transitions from a deactivated state to an activated state when the control signal is activated, and from an activated state to a deactivated state when the inductor current is equal to a reference current. The reference current corresponds to a peak value of the inductor current during the start-up. Thus, during the start-up, the duty cycle of the PWM signal increases with each cycle of the PWM signal. The PWM signal is provided to the boost converter for controlling the inductor current.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Arvind Sherigar, Samiran Dam, Ashutosh Ravindra Joharapurkar
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Patent number: 10877087Abstract: An audio system has an amplifier having first and second power stages configurable to drive a speaker, each power stage having two transistors connected in series. Each of one or more analog-to-digital converters is connected to measure a corresponding voltage drop across a corresponding transistor. A processor is connected to characterize the operation of the audio system based on the measured voltage drops. The ADC(s) and the processor can be used during start-up and/or run-time operations of the audio system to determine or detect transistor ON resistance, system lag time, speaker current, open-load faults, shorted-load faults, and short-to-Vdd/Vss faults. To avoid errors, the processor determines or detects and avoids under-drive conditions, high-frequency conditions, ripple-current periods, and lag-time periods while characterizing the system operations.Type: GrantFiled: November 21, 2019Date of Patent: December 29, 2020Assignee: NXP B.V.Inventors: Ashutosh Ravindra Joharapurkar, Arvind Sherigar, Sounak Maji
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Patent number: 10338619Abstract: A digitally-assisted voltage regulator includes a gate driver circuit and a compensation circuit. The voltage regulator digitizes the load profile, and uses the digital information to compensate for process and temperature variations. The voltage regulator outputs a regulated voltage signal and one or more control signals based on a supply voltage and a reference voltage. The gate driver circuit receives the regulated voltage signal and generates a gate driver signal. The compensation circuit receives the control signal and generates first and second compensation signals. The voltage regulator regulates a voltage level of the regulated voltage signal using the regulator compensation signal, and controls a ramp-rate of the gate driver signal using the second compensation signal.Type: GrantFiled: November 7, 2017Date of Patent: July 2, 2019Assignee: NXP B.V.Inventors: Shishir Goyal, Arvind Sherigar
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Publication number: 20190138041Abstract: A digitally-assisted voltage regulator includes a gate driver circuit and a compensation circuit. The voltage regulator digitizes the load profile, and uses the digital information to compensate for process and temperature variations. The voltage regulator outputs a regulated voltage signal and one or more control signals based on a supply voltage and a reference voltage. The gate driver circuit receives the regulated voltage signal and generates a gate driver signal. The compensation circuit receives the control signal and generates first and second compensation signals. The voltage regulator regulates a voltage level of the regulated voltage signal using the regulator compensation signal, and controls a ramp-rate of the gate driver signal using the second compensation signal.Type: ApplicationFiled: November 7, 2017Publication date: May 9, 2019Inventors: Shishir Goyal, Arvind Sherigar
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Patent number: 10234881Abstract: A voltage regulator has a slow loop for providing a regulated DC current and a fast loop for providing a transient current. Feedback information is used to monitor the output voltage and control the current used to generate the output voltage. The voltage regulator does not need a capacitor to create transient current.Type: GrantFiled: November 7, 2017Date of Patent: March 19, 2019Assignee: NXP B.V.Inventors: Shishir Goyal, Arvind Sherigar
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Patent number: 9069369Abstract: A voltage regulator is disclosed. The voltage regulator includes an operational amplifier (op-amp) and a voltage trim circuit. The op-amp is operable to receive a reference voltage at a first terminal. The op-amp also includes an output terminal. The voltage trim circuit is coupled between the output terminal and a second terminal of the op-amp. The voltage trim circuit is operable to modify an output voltage to be substantially equivalent with the reference voltage. The modification is performed by selecting an electrical current propagating pathway. An IC and a method to operate the voltage regulator is also disclosed.Type: GrantFiled: March 30, 2012Date of Patent: June 30, 2015Assignee: Altera CorporationInventors: Ping-Chen Liu, Justin Jon Philpott, Arvind Sherigar
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Patent number: 8618786Abstract: Integrated circuits with voltage regulation circuitry are provided. Voltage regulation circuitry may be powered by a core supply voltage and may not have a bandgap reference circuit. Voltage regulation circuitry may have an error amplifier in a negative feedback configuration. The error amplifier may have inputs connected to reference voltages generated by resistor strings. The resistor strings may be trimmable to provide a desired negative voltage. The desired negative voltage may be fed to the gates of transistors to help reduce leakage. The desired negative voltage may be have improved tolerance to process-voltage-temperature variations and may improve the reliability of transistors.Type: GrantFiled: August 31, 2009Date of Patent: December 31, 2013Assignee: Altera CorporationInventors: Srinivas Perisetty, Arvind Sherigar
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Patent number: 8575977Abstract: A comparator is disclosed. The comparator includes a mirror circuit that is electrically coupled to a first voltage source and a second voltage source. The first voltage source produces a first voltage and the second voltage source produces a second voltage. The comparator also includes a first positive metal oxide semiconductor (PMOS) transistor electrically coupled to the first voltage source and an output terminal. The first PMOS transistor is biased by the mirror circuit. The comparator also includes a first negative metal oxide semiconductor (NMOS) that is electrically coupled to a ground terminal and the output terminal. The first NMOS transistor is also biased by the mirror circuit. An electrical current flowing across the first NMOS transistor is mirrored from an electrical current flowing through the first PMOS transistor. A method to operate the comparator and a comparator system is also disclosed.Type: GrantFiled: March 23, 2012Date of Patent: November 5, 2013Assignee: Altera CorporationInventors: Justin Jon Philpott, Arvind Sherigar, Jeffery Chow, Ping-Chen Liu