Patents by Inventor Arvind Sridhar
Arvind Sridhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200321969Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH
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Patent number: 10727846Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: GrantFiled: September 25, 2019Date of Patent: July 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
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Publication number: 20200021301Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH
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Patent number: 10516402Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.Type: GrantFiled: December 26, 2018Date of Patent: December 24, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eric Paul Lindgren, Arvind Sridhar, Jayawardan Janardhanan
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Patent number: 10505555Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.Type: GrantFiled: December 20, 2018Date of Patent: December 10, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sinjeet Dhanvantray Parekh, Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar
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Patent number: 10498344Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: GrantFiled: December 27, 2018Date of Patent: December 3, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
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Publication number: 20190288695Abstract: A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.Type: ApplicationFiled: December 27, 2018Publication date: September 19, 2019Inventors: Henry YAO, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH, Jayawardan JANARDHANAN
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Publication number: 20190288699Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.Type: ApplicationFiled: December 20, 2018Publication date: September 19, 2019Inventors: Sinjeet Dhanvantray PAREKH, Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR
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Publication number: 20190280695Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.Type: ApplicationFiled: December 26, 2018Publication date: September 12, 2019Inventors: Eric Paul LINDGREN, Arvind SRIDHAR, Jayawardan JANARDHANAN
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Publication number: 20190280699Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: ApplicationFiled: December 27, 2018Publication date: September 12, 2019Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH
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Patent number: 9111066Abstract: A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an indication of an output clock frequency. The tool also detects selection by the user of a soft control and, as a result of detecting selection of the soft control, generates a plurality of clock tree solutions. The tool further causes a graphical form of a highlighted one of the clock tree solutions to be displayed in a second window of the GUI. An algorithm for generating the various clock tree solutions is also disclosed.Type: GrantFiled: November 14, 2013Date of Patent: August 18, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dean Kumar Banerjee, Timothy Paul Toroni, Robert Charles Farrow, Jr., Valerie Way Chang, Brandon Micah Hoppe, Arvind Sridhar, Makram Mounzer Mansour, Khang Duy Nguyen
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Publication number: 20150135152Abstract: A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an indication of an output clock frequency. The tool also detects selection by the user of a soft control and, as a result of detecting selection of the soft control, generates a plurality of clock tree solutions. The tool further causes a graphical form of a highlighted one of the clock tree solutions to be displayed in a second window of the GUI. An algorithm for generating the various clock tree solutions is also disclosed.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Dean Kumar Banerjee, Timothy Paul Toroni, Robert Charles Farrow, JR., Valerie Way Chang, Brandon Micah Hoppe, Arvind Sridhar, Makram Mounzer Mansour, Khang Duy Nguyen
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Patent number: 8164367Abstract: A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal line of an image to be generated based on the imaging clock signal. The modulation circuit generates a modulation signal based on the determined number of pixels and the clock signal generator spreads the frequency of the imaging clock signal across a frequency range based on the modulation signal. In this way, the clock signal generator reduces electromagnetic interference in the imaging clock signal. In further embodiments, the clock signal generator generates an adjustment signal for adjusting the frequency range based on the frequency of the reference clock signal and the frequency of the imaging clock signal.Type: GrantFiled: January 15, 2009Date of Patent: April 24, 2012Assignee: Integrated Device Technology, Inc.Inventors: Jagdeep Bal, Arvind Sridhar