Abstract: Techniques and apparatus for transmission and reception with partial allocation in orthogonal frequency division multiple access (OFDMA)/single-carrier frequency division multiple access (SC-FDMA) systems are provided. One technique includes determining first parameter(s) to apply to transmission/receive processing of a signal, based in part on a resource allocation for the signal. The resource allocation is partitioned out of a larger system bandwidth. Second parameter(s) to apply to the transmission/receive processing are determined based at least in part on the first parameter(s). Transmission/receive processing of the signal is performed in accordance with the first and second parameters.

Abstract: There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a narrowband communication frame structure comprising a FDD mode or a TDD mode and a particular TDD frame structure for narrowband communications from a group of narrowband TDD frame structures. The apparatus may determine a periodicity, subframe number, and transmission sequence associated with a SSS based at least in part on the narrowband TDD frame structure. The apparatus may transmit the SSS using the narrowband TDD frame structure determined for the narrowband communications.

Abstract: There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a narrowband communication frame structure comprising a FDD frame structure or a TDD frame structure and a narrowband TDD frame structure configuration for narrowband communications from a group of narrowband TDD frame structures configurations. The apparatus may determine one or more narrowband carriers and subframes within the one or more narrowband carriers to transmit at least one of a BCH or a SIB1 based on the narrowband communication frame structure or the TDD frame structure configuration. The apparatus may transmit a PSS, an SSS, and at least one of a BCH or an SIB1 using the narrowband TDD frame structure determined for the narrowband communications.

Abstract: There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a bandwidth for narrowband communications. The apparatus may determine a narrowband TDD frame structure for the narrowband communications. In one aspect, the narrowband TDD frame structure may include at least one of two or more contiguous downlink subframes, or one or more flexible subframes that can be configured as either a downlink subframe or an uplink subframe. The apparatus may communicate with a UE using the narrowband TDD frame structure determined for the narrowband communications.

Abstract: There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a narrowband TDD frame structure for narrowband communications from a group of narrowband TDD frame structures. In one aspect, the narrowband TDD frame structure may include a set of downlink subframes and more than one special subframe. The apparatus may determine a set of narrowband carriers and a minimum set of subframes on the set of narrowband carriers based at least in part on the set of downlink subframes and more than one special subframe on which a NRS should be transmitted. The apparatus may transmit the NRS using the narrowband TDD frame structure determined for the narrowband communications.

Abstract: There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a TDD mode for narrowband communications. The apparatus may determine a TDD frame structure for the narrowband communications from a group of narrowband TDD frame structures. In one aspect, at least one common subframe in each narrowband TDD frame structure in the group of narrowband TDD frame structures may be configured as a downlink subframe. The apparatus may transmit a PSS using the at least one common subframe in the narrowband TDD frame structure determined for the narrowband communications.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

Abstract: A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract: A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.

Abstract: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

Abstract: Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions.

Abstract: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

Abstract: Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category.

Abstract: Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values.

Abstract: Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

Abstract: A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.