Abstract: A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage Ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.

Abstract: System and method for supporting scalable bitmap based P_Key table in a high performance computing environment. A method can provide, at least one subnet comprising one or more switches, a plurality of host channel adapters, and a plurality of end nodes. The method can associate the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value. The method can associate each of the one or more switches with a bitmap based P_Key table of a plurality of bitmap based P_Key tables. The method can associate each of the host channel adapters with a bitmap based P_Key table of the plurality of bitmap based P_Key tables.

Abstract: A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

Abstract: Methods for improving end-to-end congestion reaction using adaptive routing and congestion-hint based throttling for IP-routed datacenter networks and associated apparatus. In connection with forwarding packets between sending and receiving endpoints coupled to one or more networks, one or more network switches are configured to detect current or approaching congestion conditions, generate congestion notification packets (CNPs), and return the CNPs to sending endpoints. The CNPs may be routed using one or more adaptive routing mechanisms to forward the CNPs along non-congested paths or may be forwarded along a fastest path to a sender. The CNPs further may comprise meta-data including a flow identifier associated with a packet sent from an endpoint, a congestion level for the flow, and a timestamp.

Abstract: A system for facilitating RDMA transmit flow scheduling and pacing is disclosed. The system may determine a set of groups. The groups may be associated with a range of transmission rates. The system may determine a transmission rate of a queue pair. The system may assign the QP to a first group of the set of groups. The transmission rate of the QP may be within the range of transmission rates of the first group. The system may determine an available QP of at least one group from the set of groups. The system may schedule transmission, by an arbiter, of the available QP. The system may transmit, by the arbiter, a message associated with the available QP.

Abstract: A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.

Abstract: A system for Remote Direct Memory Access incast congestion management is provided. The system may access one or more receive work queue entities (RWQEs) associated with one or more send work queue entities (SWQEs), determine a transmission rate based on an available bandwidth and a number of transmitter devices associated with the one or more SWQEs, and transmit a rate control notification (RCN) message to a transmitter device associated with a send work queue entity of the one or more SWQEs, wherein the rate control notification message comprises the determined transmission rate.

Abstract: Systems, apparatuses and methods provide technology that identifies a message that is to be transmitted across a network, divides the message into a plurality of portions that are arranged in a first order, and generates a plurality of packets based on the plurality of portions. The technology maps different network paths for the plurality of packets to be transmitted to a destination, sets headers of the plurality of packets to represent the first order and the different network paths, transmits the plurality of packets over the network in an out-of-order fashion to the destination based on the headers, and arranges the plurality of transmitted packets into the first order based on the headers of the plurality of packets.

Abstract: A system for adapting to a partially unhealthy network and bypassing failures associated with the network is provided. The system may enable determining a designated network path configured to transfer traffic data from a first communication device, via one or more network switches, to a second communication device. The system may enable determining at least one network failure, associated with the network path, causing at least a subset of the traffic data to be blocked along the network path. The system may enable determining one or more tracker windows associated with one or more other network paths that are available to transfer traffic content. The system may enable selecting at least one network path of the one or more other network paths to transfer the at least the subset of the traffic data to the second communication device.

Abstract: Embodiments detect stops by an entity on a pre-planned trip including a plurality of stops and a planned sequence of stops, each stop including a geofence boundary. For each stop, embodiments add an arrival transition region extending inward from the geofence boundary. Embodiments receive a first geo-location message indicating a first location and corresponding to a first time for the entity and determine whether the first location falls within a first arrival transition region corresponding to a first stop having a first geofence boundary. When the first location falls within the first arrival transition region, embodiments wait for a predefined transitional time period. During the predefined transitional time period, when a second geo-location message is received indicating a second location inside the first geofence boundary and outside the first arrival transition region, the first time is determined to be an arrival time for the first stop.

Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer.

Abstract: Disclosed are autonomous vehicles that may autonomously navigate at least a portion of a route defined by a service request allocator. The autonomous vehicle may, at a certain portion of the route, request remote assistance. In response to the request, an operator may provide input to a console that indicates control positions for one or more vehicle controls such as steering position, brake position, and/or accelerator position. A command is sent to the autonomous vehicle indicating how the vehicle should proceed along the route. When the vehicle reaches a location where remote assistance is no longer required, the autonomous vehicle is released from manual control and may then continue executing the route under autonomous control.

Abstract: According to examples, a system for aligning a plurality of variously encoded content streams is described. The system may include a processor and a memory storing instructions. The processor, when executing the instructions, may cause the system to receive a request to transmit one or more packets of a message over a network, upon receive the request, designate a message sequence number (MSN) for the message, and upon receive the request, designate a packet sequence number (PSN) for one or more packets of the message.

Abstract: A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.

Abstract: System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.

Abstract: According to examples, a selective acknowledgement framework may be implemented within a communication system for efficient communication of acknowledgement packets. A plurality of data packets generated from a message may be transmitted as a segment of data packets to a receiver which generates an acknowledgement packet for the segment of data packets. A compact format of acknowledgement (ACK) or negative acknowledgement (NACK) for the segment of data packets may be implemented in the acknowledgement packet via bits of a selective acknowledgement bit vector. Based on the other values also conveyed in the acknowledgement packet, the transmitter may identify those data packets that were properly received and the data packets that need to be re-transmitted.

Abstract: Systems and methods are provided for obtaining data to be secured based on a secret sharing technique, the data being associated with a file identifier and a split specification that includes at least a number of splits n and a minimum number of splits m required for reconstructing the data, and a Repeatable Random Sequence Generator (RRSG) RRSG scheme. An RRSG state can be initialized based at least in part on a given data transformation key to provide repeatable sequence of random bytes. For every m bytes of data: a polynomial whose coefficients are determined based at least in part on m bytes of the data and a portion of the repeatable sequence of random bytes can be determined; the polynomial can be evaluated at n unique values determined by a portion of repeatable sequence of random bytes to generate n bytes. Each byte can be stored into one of the n split stores.

Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.

Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.