Patents by Inventor Arvind Srinivasan

Arvind Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141059
    Abstract: Provided herein are heavy chain constant regions (referred to as “modified heavy chain constant regions”), or functionally equivalent fragments thereof, that enhance biological properties of antibodies relative to the same antibodies in unmodified form. An exemplary modified heavy chain constant region includes an IgG2 hinge and three constant domains (i.e., CH1, CH2, and CH3 domains), wherein one or more of the constant region domains are of a non-IgG2 isotype (e.g., IgG1, IgG3 or IgG4). The heavy chain constant region may comprise wildtype human IgG domain sequences, or variants of these sequences. Also provided herein are methods for enhancing certain biological properties of antibodies that comprise a non-IgG2 hinge, such as internalization, agonism and antagonism, wherein the method comprises replacing the non-IgG2 hinge of the antibody with an IgG2 hinge.
    Type: Application
    Filed: August 30, 2023
    Publication date: May 2, 2024
    Inventors: Nils LONBERG, Alan J. KORMAN, Mark J. SELBY, Bryan C. BARNHART, Aaron P. YAMNIUK, Mohan SRINIVASAN, Karla A. HENNING, Michelle Minhua HAN, Ming LEI, Liang SCHWEIZER, Sandra V. HATCHER, Arvind RAJPAL
  • Patent number: 11916800
    Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: David Arditti Ilitzky, John Greth, Robert Southworth, Karl S. Papadantonakis, Bongjin Jung, Arvind Srinivasan
  • Patent number: 11884293
    Abstract: Disclosed are autonomous vehicles that may autonomously navigate at least a portion of a route defined by a service request allocator. The autonomous vehicle may, at a certain portion of the route, request remote assistance. In response to the request, an operator may provide input to a console that indicates control positions for one or more vehicle controls such as steering position, brake position, and/or accelerator position. A command is sent to the autonomous vehicle indicating how the vehicle should proceed along the route. When the vehicle reaches a location where remote assistance is no longer required, the autonomous vehicle is released from manual control and may then continue executing the route under autonomous control.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: January 30, 2024
    Assignee: Uber Technologies, Inc.
    Inventors: Arvind Srinivasan, Samann Ghorbanian-Matloob, Sean Shanshi Chen, Eli Schleifer, Shelley Bower, Patrick Willett
  • Publication number: 20230403237
    Abstract: According to examples, a system for aligning a plurality of variously encoded content streams is described. The system may include a processor and a memory storing instructions. The processor, when executing the instructions, may cause the system to receive a request to transmit one or more packets of a message over a network, upon receive the request, designate a message sequence number (MSN) for the message, and upon receive the request, designate a packet sequence number (PSN) for one or more packets of the message.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Applicant: Meta Platforms, Inc.
    Inventors: Arvind SRINIVASAN, Nicolaas Johannes Viljoen, Pankaj Kansal, Ashay Narsale
  • Publication number: 20230385138
    Abstract: A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: Pankaj Kansal, Arvind Srinivasan, Harikrishna Madadi Reddy, Naader Hasani
  • Patent number: 11824749
    Abstract: System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: November 21, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Bjørn Dag Johnsen, Arvind Srinivasan, Brian Manula
  • Publication number: 20230370203
    Abstract: According to examples, a selective acknowledgement framework may be implemented within a communication system for efficient communication of acknowledgement packets. A plurality of data packets generated from a message may be transmitted as a segment of data packets to a receiver which generates an acknowledgement packet for the segment of data packets. A compact format of acknowledgement (ACK) or negative acknowledgement (NACK) for the segment of data packets may be implemented in the acknowledgement packet via bits of a selective acknowledgement bit vector. Based on the other values also conveyed in the acknowledgement packet, the transmitter may identify those data packets that were properly received and the data packets that need to be re-transmitted.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Meta Platforms, Inc.
    Inventors: Arvind SRINIVASAN, Zeeshan Altaf LOKHANDWALA, Pankaj KANSAL, Nicolaas Johannes VILJOEN
  • Patent number: 11736457
    Abstract: Systems and methods are provided for obtaining data to be secured based on a secret sharing technique, the data being associated with a file identifier and a split specification that includes at least a number of splits n and a minimum number of splits m required for reconstructing the data, and a Repeatable Random Sequence Generator (RRSG) RRSG scheme. An RRSG state can be initialized based at least in part on a given data transformation key to provide repeatable sequence of random bytes. For every m bytes of data: a polynomial whose coefficients are determined based at least in part on m bytes of the data and a portion of the repeatable sequence of random bytes can be determined; the polynomial can be evaluated at n unique values determined by a portion of repeatable sequence of random bytes to generate n bytes. Each byte can be stored into one of the n split stores.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 22, 2023
    Assignee: SplitByte Inc.
    Inventor: Arvind Srinivasan
  • Patent number: 11722438
    Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: John Greth, Arvind Srinivasan, Robert Southworth, David Arditti Ilitzky, Bongjin Jung, Gaspar Mora Porta
  • Patent number: 11700209
    Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Robert Southworth, Karl S. Papadantonakis, Mika Nystroem, Arvind Srinivasan, David Arditti Ilitzky, Jonathan Dama
  • Patent number: 11641326
    Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Karl S. Papadantonakis, Robert Southworth, Arvind Srinivasan, Helia A. Naeimi, James E. McCormick, Jr., Jonathan Dama, Ramakrishna Huggahalli, Roberto Penaranda Cebrian
  • Patent number: 11621918
    Abstract: A transmitter can manage when a transmit queue is permitted to transmit and an amount of data permitted to be transmitted. After a transmit queue is permitted to transmit, the transmit queue can be placed in a sleep state if the transmit queue has exceeded its permitted data transmission quota. The wake time of the transmit queue can be scheduled based on a token accumulation rate for the transmit queue. The token accumulation rate can be increased if the transmit queue has other data to transmit after the data transmission. The token accumulation rate can be decreased if the transmit does not have other data to transmit.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Ben-Zion Friedman, Simoni Ben-Michael, Arvind Srinivasan, Tony Hurson, Adam Conyers, Hemanth Krishnan
  • Patent number: 11616723
    Abstract: At a network-connected device, congestion at an egress queue can be detected. A potential source of congestion can be identified based on characteristics of a packet that caused the egress queue to become congested. The source of congestion can be a congestion group of transmitters. A group congestion message can be sent to the group of transmitters. The message can identify the packet that caused the egress queue to become congested. Transmitters can respond to the message by reducing their peak transmission rate.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Ben-Zion Friedman, Simoni Ben-Michael, Arvind Srinivasan, Tony Hurson, Adam Conyers, Hemanth Krishnan
  • Patent number: 11598376
    Abstract: A joint assembly includes a first member having splines formed therein. A second member includes splines formed thereon and is coupled to the first member. The splines of the first member engage the splines of the second member. An access window is formed on the first member. A ring retains the first member to the second member. A seal extends across a joint between the first member and the second member and covers the access window. A portion of the ring is accessible through the access window following removal of the seal, where the ring can be manipulated to release the first member from the second member.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 7, 2023
    Assignee: NEAPCO INTELLECTUAL PROPERTY HOLDINGS, LLC
    Inventors: Michael Walter Hopson, Arvind Srinivasan, Michael Peter Kinsella
  • Patent number: 11575609
    Abstract: A switch or network interface can detect congestion caused by a flow of packets. The switch or network interface can generate a congestion hint packet and send the congestion hint packet directly to a source transmitter of the flow of packets that caused the congestion. The congestion hint packet can include information that the source transmitter can use to determine a remedial action to attempt to alleviate or stop congestion at the switch or network interface. For example, the transmitter can reduce a transmit rate of the flow of packets and/or select another route for the flow of packets. Some or all switches or network interfaces between the source transmitter and a destination endpoint can employ flow differentiation whereby a queue is selected to accommodate for a flow's sensitivity to latency.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Arvind Srinivasan, Ramakrishna Huggahalli, Parthasarathy Sarangam, Sunil Ahluwalia, Mrittika Ganguli, Malek Musleh
  • Patent number: 11531752
    Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Akeem Abodunrin, Lev Faerman, Scott Dubal, Suyog Kulkarni, Anjali Singhai Jain, Eliel Louzoun, Nrupal Jani, Yadong Li, Eliezer Tamir, Arvind Srinivasan, Ben-Zion Friedman
  • Publication number: 20220400074
    Abstract: A system includes reception of an instruction to send a message to a computer server, determination of a plurality of segments of the message, determination, for each of the plurality of segments, of a network path from a plurality of network paths to the computer server based on performance-related characteristics of the plurality of network paths, and assignment, for each of the plurality of segments, of the segment to a transmission queue associated with the network path determined for the segment.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Inventors: Arvind SRINIVASAN, Nisheeth SRIVASTAVA
  • Patent number: 11509592
    Abstract: A network endpoint receiver controls packet flow from a transmitter. Packets are received via a network in packet traffic according to a push mode, where the transmitter controls pacing of transmitting the packets. Characteristics related to the packet traffic are monitored at the receiver. The monitored characteristics are compared to reception performance parameters, and based on the comparison, a decision is made to switch from the push mode to a pull mode for controlling the packet flow. The receiver transmits a pull mode request packet to the transmitter, where the pull mode request packet indicates a pacing of subsequent packets transmitted by the transmitter to the receiver in accordance with the pull mode. Pacing of further transmitted packets may be controlled by subsequent pull mode request packets sent over time to the transmitter by the receiver. Similarly, the receiver may control additional transmitters to transmit at equal or different rates.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 22, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Arvind Srinivasan, Nisheeth Srivastava, David Andreas Sidler
  • Publication number: 20220364607
    Abstract: A joint assembly includes a first member having splines formed therein. A second member includes splines formed thereon and is coupled to the first member. The splines of the first member engage the splines of the second member. An access window is formed on the first member. A ring retains the first member to the second member. A seal extends across a joint between the first member and the second member and covers the access window. A portion of the ring is accessible through the access window following removal of the seal, where the ring can be manipulated to release the first member from the second member.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Michael Walter Hopson, Arvind Srinivasan, Michael Peter Kinsella
  • Patent number: 11501097
    Abstract: A barcoded end facet printed photonic chip includes: an optically transparent direct laser writing substrate including a transverse waveguide writing surface to receive a direct write laser light for off-axis direct write laser printing and a facet surface to receive the direct write laser light for on-axis direct write laser printing of a barcode-guided direct laser written optical coupling on the facet surface; a waveguide disposed in the optically transparent direct laser writing substrate and in optical communication with the facet surface; and an optically visible bulk impregnated barcode disposed in the optically transparent direct laser writing substrate arranged proximate to the waveguide and in optical communication with the facet surface.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 15, 2022
    Assignee: GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Kartik Arvind Srinivasan, Edgar F. Perez