Patents by Inventor Arvind Sudarsanam

Arvind Sudarsanam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11366647
    Abstract: Systems, apparatuses and methods may provide for technology that detects one or more local variables in source code, wherein the local variable(s) lack dependencies across iterations of a loop in the source code, automatically generate pipeline execution code for the local variable(s), and incorporate the pipeline execution code into an output of a compiler. In one example, the pipeline execution code includes an initialization of a pool of buffer storage for the local variable(s).
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Rajiv Deodhar, Sergey Dmitriev, Daniel Woodworth, Rakesh Krishnaiyer, Kent Glossop, Arvind Sudarsanam
  • Publication number: 20200257510
    Abstract: Systems, apparatuses and methods may provide for technology that detects one or more local variables in source code, wherein the local variable(s) lack dependencies across iterations of a loop in the source code, automatically generate pipeline execution code for the local variable(s), and incorporate the pipeline execution code into an output of a compiler. In one example, the pipeline execution code includes an initialization of a pool of buffer storage for the local variable(s).
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Rajiv Deodhar, Sergey Dmitriev, Daniel Woodworth, Rakesh Krishnaiyer, Kent Glossop, Arvind Sudarsanam
  • Patent number: 9658829
    Abstract: Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Karthikeyan Vaithianathan, Arvind Sudarsanam
  • Patent number: 8281297
    Abstract: A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: October 2, 2012
    Assignee: Arizona Board of Regents
    Inventors: Aravind R. Dasu, Ali Akoglu, Arvind Sudarsanam, Sethuraman Panchanathan
  • Publication number: 20110093518
    Abstract: Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 21, 2011
    Inventors: Karthikeyan Vaithianathan, Arvind Sudarsanam
  • Publication number: 20070198971
    Abstract: A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 23, 2007
    Inventors: Aravind Dasu, Ali Akoglu, Arvind Sudarsanam, Sethuraman Panchanathan