Patents by Inventor Arvindh Rajasekaran

Arvindh Rajasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11650233
    Abstract: A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Neha Bhargava, Arvindh Rajasekaran, Anup Deka
  • Publication number: 20220376515
    Abstract: A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Applicant: Intel Corporation
    Inventors: Jagadish Singh, Rohit Parakkal, Tarakesava Reddy K, Arvind S, Arvindh Rajasekaran, Raghavendra R. Rao
  • Publication number: 20210389353
    Abstract: A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.
    Type: Application
    Filed: December 16, 2020
    Publication date: December 16, 2021
    Applicant: Intel Corporation
    Inventors: Neha Bhargava, Arvindh Rajasekaran, Anup Deka
  • Patent number: 10250052
    Abstract: A method, an apparatus, and a computer-readable medium for battery charging are provided. The apparatus determines a level of a charge current for charging a battery based on a user preference. The apparatus determines a number of rest periods in the charge current, wherein during the rest periods, the apparatus is configured to perform at least one of setting the charge current to zero or discharging the battery. The apparatus charges the battery with the determined level of the charge current and the determined number of rest periods.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Radhika Bharath Patil, Arvindh Rajasekaran
  • Patent number: 9935546
    Abstract: Power supplies combining a switching-mode power supply in parallel with a current source can improve maximum load current capability. The current source can be turned on, or the amount of current supplied by the current source increased, when there is a heavy load current demand, for example, when the load current demand is more than the current rating of the switching-mode power supply. The duty cycle of the output stage of the switching-mode power supply can be used to determine the load current demand. The current source may increase the maximum output current of the power supply beyond the maximum output current of the switching-mode power supply. For example, the current source may add 0.5 A to the current capability of a 2.5 A switching-mode power supply.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 3, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Srikanth Jatavallabhula, Anand Kudari, Arvindh Rajasekaran
  • Publication number: 20170222554
    Abstract: Power supplies combining a switching-mode power supply in parallel with a current source can improve maximum load current capability. The current source can be turned on, or the amount of current supplied by the current source increased, when there is a heavy load current demand, for example, when the load current demand is more than the current rating of the switching-mode power supply. The duty cycle of the output stage of the switching-mode power supply can be used to determine the load current demand. The current source may increase the maximum output current of the power supply beyond the maximum output current of the switching-mode power supply. For example, the current source may add 0.5 A to the current capability of a 2.5 A switching-mode power supply.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 3, 2017
    Inventors: Srikanth JATAVALLABHULA, Anand KUDARI, Arvindh RAJASEKARAN
  • Publication number: 20170163046
    Abstract: A method, an apparatus, and a computer-readable medium for battery charging are provided. The apparatus determines a level of a charge current for charging a battery based on a user preference. The apparatus determines a number of rest periods in the charge current, wherein during the rest periods, the apparatus is configured to perform at least one of setting the charge current to zero or discharging the battery. The apparatus charges the battery with the determined level of the charge current and the determined number of rest periods.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Radhika Bharath PATIL, Arvindh RAJASEKARAN
  • Publication number: 20150268678
    Abstract: The disclosed systems and methods for current management can be used with system-on-a-chip (SoC) integrated circuits in, for example, battery-powered portable devices. The current management provides detection of supply current levels from a power management integrated circuit (PMIC) to an SoC. The PMIC signals, for example, using interrupts, the SoC when the supply current levels exceed thresholds. The SoC can then alter its operations to avoid exceeding the current capability of the PMIC. The current management can avoid the SoC experiencing a functional failure due to loss of power during high current conditions. Additionally, development methods can be used to optimize a system for various conditions besides the traditional worst-case design commonly used.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Guolei Yu, Arvindh Rajasekaran, Amy Derbyshire, Ching Chang Shen