Patents by Inventor Arvindhkumar Lalam

Arvindhkumar Lalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interleaving in multi-level data cache on memory bus
    Patent number: 11698873
    Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 11, 2023
    Assignee: nCorium
    Inventor: Arvindhkumar Lalam
  • MULTI-LEVEL DATA CACHE AND STORAGE ON A MEMORY BUS
    Publication number: 20210034555
    Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 4, 2021
    Inventor: Arvindhkumar Lalam
  • Multi-level data cache and storage on a memory bus
    Patent number: 10747694
    Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 18, 2020
    Assignee: nCorium
    Inventor: Arvindhkumar Lalam
  • Non-volatile dual in-line memory module (NVDIMM) multichip package
    Patent number: 10199364
    Abstract: A single multichip package is provided, comprising: a substrate having opposing upper and lower surfaces. A first die is mounted on the upper surface of the substrate and includes one or more non-volatile memory devices. A second die is mounted on the upper surface of the substrate, and includes at least one of: (a) a non-volatile memory controller that facilitates transfer of data to/from the one or more non-volatile memory devices, (b) a register clock driver for volatile memory devices, and/or (c) one or more multiplexer switches configured to switch between two or more of the volatile memory devices. A plurality of wire bonds connect the first and second dies. A plurality of solder balls are located on the lower surface of the substrate for mounting the single multichip package to a printed circuit board, the plurality of solder balls electrically coupled to the first die and the second die.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 5, 2019
    Assignee: SANMINA CORPORATION
    Inventors: Arvindhkumar Lalam, Alec C. Shen
  • MULTI-LEVEL DATA CACHE AND STORAGE ON A MEMORY BUS
    Publication number: 20170351626
    Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 7, 2017
    Inventor: Arvindhkumar Lalam
  • NON-VOLATILE DUAL IN-LINE MEMORY MODULE (NVDIMM) MULTICHIP PACKAGE
    Publication number: 20170338213
    Abstract: A single multichip package is provided, comprising: a substrate having opposing upper and lower surfaces. A first die is mounted on the upper surface of the substrate and includes one or more non-volatile memory devices. A second die is mounted on the upper surface of the substrate, and includes at least one of: (a) a non-volatile memory controller that facilitates transfer of data to/from the one or more non-volatile memory devices, (b) a register clock driver for volatile memory devices, and/or (c) one or more multiplexer switches configured to switch between two or more of the volatile memory devices. A plurality of wire bonds connect the first and second dies. A plurality of solder balls are located on the lower surface of the substrate for mounting the single multichip package to a printed circuit board, the plurality of solder balls electrically coupled to the first die and the second die.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 23, 2017
    Inventors: Arvindhkumar Lalam, Alec C. Shen