Abstract: An interposer includes a first substrate including first bulk material having a first TSV extending through the first bulk material, and a second substrate including second bulk material having a second TSV extending through the second bulk material and a wiring plane formed on the second bulk material in electrical contact with the second TSV. A join interface connects the first and second substrates such that the wiring plane of the first substrate physically contacts the second substrate and the first TSVs are electrically connected to the second TSV through the wiring plane. A passive electrical device integrated within the interposer at the join interface, wherein the passive electrical device is electrically connected to the wiring plane.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. Also provided is a second interposer substrate including a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method includes connecting a passive electrical device to at least one of the first and second interposer substrates. The first interposer substrate is joined to the second interposer substrate such that the passive electrical device is provided between the first and second interposer substrates and the wiring plane is provided as an interface wiring plane between the first and second bulk materials.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. Also provided is a second interposer substrate including a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method includes connecting a passive electrical device to at least one of the first and second interposer substrates. The first interposer substrate is joined to the second interposer substrate such that the passive electrical device is provided between the first and second interposer substrates and the wiring plane is provided as an interface wiring plane between the first and second bulk materials.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.

Abstract: A method of manufacturing an integrated circuit having a multilayer structure where the method includes the steps of depositing a thin layer of low temperature oxide (LTO) on top of conductors and then spinning and curing a thin layer of spin-on-glass to planarize the surface of the device. This structure is then plasma etched to remove the spin-on-glass and a portion of the LTO at approximately the same rate. The structure is then dipped in a mild potassium hydroxide solution to completely remove the SOG material, even from the crevices and gaps which are present on the surface. This enables the device to be manufactured free of any organic substances from the SOG in the body of the structure. A passivation layer can now be deposited to protect the underlying circuitry from ionic contamination, water vapor penetration and handling.

Abstract: A process for minimizing bird's beak in local oxidation of silicon which is compatible with high density (VLSI) semiconductor devices is disclosed. A pad oxide is nitridized using rapid thermal nitridization, which works quickly with minimal thermal cycling of the wafer. A silicon nitride film is then deposited over the nitridized oxide. Both films are exposed to dry plasma etching which gives more consistent results than wet methods. The field oxide is then grown and finally the masking films of the nitridized oxide and silicon nitride are removed, whereby field oxides are grown with minimal bird's beak, and minimal damage to the wafer with a small number of steps. The pad oxide may be grown in the same rapid thermal annealer used for the rapid thermal nitridization. Both cycles (pad oxide growth and nitridization of the pad oxide) can be integrated to "one" cycle and performed sequentially in the same rapid thermal annealer to increase throughput and improve device quality.