Abstract: An apparatus and a method for accelerating Cyclic Redundancy Check (CRC) calculations. The apparatus includes a CRC circuit and an accelerator for accelerating the computation of the CRC code so that the CRC code is outputted immediately after the last bit of the input data stream is inserted to the CRC machine, thereby reducing the time required to compute the CRC calculation. The apparatus accelerates the CRC calculation by eliminating the need to append zeros to the input data stream.

Abstract: A method for improving CdZnTe-based gamma-ray detectors is presented. A CdZnTe detector/crystal is exposed to acoustic waves. After exposure to acoustic waves, the CdZnTe gamma-detector gains higher resistivity and exhibits better spectral resolution and greater sensitivity. Further, when a batch of detectors is made according to the method of the present invention, the properties of the crystals are more homogenous, allowing for cheaper and more standardized detectors.

Abstract: A method for improving CdZnTe-based gamma-ray detectors is presented. A CdZnTe detector/crystal is exposed to acoustic waves. After exposure to acoustic waves, the CdZnTe gamma-detector gains higher resistivity and exhibits better spectral resolution and greater sensitivity. Further, when a batch of detectors is made according to the method of the present invention, the properties of the crystals are more homogenous, allowing for cheaper and more standardized detectors.

Abstract: An apparatus and a method for accelerating Cyclic Redundancy Check (CRC) calculations. The apparatus includes a CRC circuit and an accelerator for accelerating the computation of the CRC code so that the CRC code is outputted immediately after the last bit of the input data stream is inserted to the CRC machine, thereby reducing the time required to compute the CRC calculation. The apparatus accelerates the CRC calculation by eliminating the need to append zeros to the input data stream.

Abstract: A method and system for generating a pseudo-random bit series based on a given polynomial of order N, for M parallel communication lines using a machine comprising: N flip-flop machines and logic circuit. The flip-flop machines is initialized according to a given series of N bits. The logic circuit calculates a series of the next M+N tits using the N flip flop machines as function of the current N bit series wherein the function is based on two pre-generated equations. These equations are generated by recursive calculation of matrix array of order N*M according the given polynomial equation.