Abstract: A serial communications protocol is provided that has optional link initialization features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional serial communications link features are implemented are able to perform the lane polarity reversal and lane order reversal functions. Integrated circuits in which the optional serial communications link features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Abstract: A serial communications protocol is provided that has mandatory features such as an idle code feature and optional features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature, an optional clock tolerance compensation feature, an optional flow control feature, and an optional retry-on-error feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional features are implemented are able to perform the associated functions. Integrated circuits in which the optional features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Abstract: Integrated circuits compliant with a serial communications protocol with optional features are provided. The optional features include control plane features such as flow control, retry-on-error, clock tolerance compensation, and idle codes and include data path features such as streaming and packetized data modes, configurable data ports and user-defined data channel multiplexing. An integrated circuit compliant with the protocol can transmit streaming data with or without clock tolerance compensation codes. A priority data port can be used to implement retry-on-error functions while user-defined data channels carry user data. The data ports can be individually configured to perform different levels of cyclic redundancy checking. Logic design tools are used to create compliant circuits and systems.

Abstract: Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.

Abstract: A serial communications protocol with optional and adjustable data link layer and physical layer features is provided. A logic design tool for designing circuits compliant with the protocol is also provided. Using the logic design tool, desired optional protocol features may be included to enhance circuit functionality and undesired optional protocol features may be omitted to conserve circuit resources. The logic design tool may include design aids related to retry-on-error timeout calculations, FIFO sizing, transmitter and receiver circuit parameters, and other design parameters. A user of the logic design tool can view information provided by the logic design tool's design aids and can make design selections.

Abstract: An integrated circuit includes a debugging unit which uses a multi-master general purpose bus within the IC to perform debugging functions. The storage elements of the IC are mapped into the address space of the general purpose bus. The debugging unit can operate as a bus master and read from or write to the storage elements of the integrated circuit directly with the general purpose bus. Thus, the integrated circuit can be rapidly configured for testing and debugging. Furthermore, the debugging unit can work with a breakpoint unit on the IC to detect and analyze specific situations on the IC.

Abstract: The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line including a programmable logic device (PLD) array, at least one input pin and at least one databus macrocell. The input pin is connected to the PLD array and is connectable to the address bus. The databus macrocell is connected to the PLD array and to an external unit and is also connectable to the data bus, the read line and the write line. The databus directly accesses the databus macrocell.

Abstract: An embodiment of this invention provides an integrated circuit (IC) having a configurable peripheral port which includes an input/output pin, a multiplexer coupled to the input/output pin, volatile configuration bits to control the multiplexer, and non-volatile configuration bits to control the multiplexer and override the volatile configuration bits. One embodiment of an IC also includes a peripheral port as above and functional units, such as programmable array logic (PAL) and erasable programmable read only memory (EPROM), coupled to the multiplexer. In another embodiment, a non-volatile configuration bit from a functional unit configures an input/output pin when the configuration bit is not needed by the functional unit.

Abstract: Page logic, which is coupled to a programmable array decoder, allows for expansion of memory address space depending on the number of bits in a page register. The programmable array decoder has a "don't care" function which allows the user to be independent of the page mode.