Patents by Inventor Asa Frye
Asa Frye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11873249Abstract: A fibrous ceramic preform includes a plurality of ceramic fibers, a first amorphous layer, and an interfacial coating layer. The interfacial coating layer includes an anisotropic region adjacent the at least one amorphous layer, and an isotropic region on a side of the anisotropic region opposite the at least one amorphous layer.Type: GrantFiled: May 6, 2022Date of Patent: January 16, 2024Assignee: RTX CorporationInventors: Asa Frye, Cristal Chan, Daniel L. Becerra
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Publication number: 20230357093Abstract: A fibrous ceramic preform includes a plurality of ceramic fibers, a first amorphous layer, and an interfacial coating layer. The interfacial coating layer includes an anisotropic region adjacent the at least one amorphous layer, and an isotropic region on a side of the anisotropic region opposite the at least one amorphous layer.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Asa Frye, Cristal Chan, Daniel L. Becerra
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Patent number: 8741773Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.Type: GrantFiled: January 8, 2010Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Asa Frye, Andrew Simon
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Patent number: 8637925Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.Type: GrantFiled: February 29, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Asa Frye, Andrew Simon
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Publication number: 20120153359Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Asa Frye, Andrew Simon
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Patent number: 8101518Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: GrantFiled: June 11, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Publication number: 20110169058Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Asa Frye, Andrew Simon
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Patent number: 7759208Abstract: Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.Type: GrantFiled: March 27, 2009Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Asa Frye, Christian Lavoie, Ahmet S. Ozcan, Donald R. Wall
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Patent number: 7544610Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: GrantFiled: September 7, 2004Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Publication number: 20080274611Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: ApplicationFiled: June 11, 2008Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman