Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract: A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

Abstract: In accordance with the invention, there are semiconductor devices and methods for making semiconductor devices and film stacks in an integrated circuits. The method of making a semiconductor device can comprise forming a semiconductor structure comprising at least one copper interconnect, forming an etch stop bi-layer comprising a first layer and a second layer, wherein the first layer comprising silicon nitride is disposed over the semiconductor structure comprising at least one copper interconnect, and the second layer comprising silicon oxy-carbide is disposed over the first layer, and depositing a dielectric layer over the etch stop bi-layer.

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract: The present invention provides a method of forming a metal seed layer 100. The method comprises physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.

Abstract: The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the barrier material 200.

Abstract: A method is disclosed to form a seed layer for an integrated circuit. The method may include depositing a metal seed layer (106) over a barrier layer (104) such that the metal seed layer (106) has a greater thickness along a top surface portion (114) of at least one recessed feature (102) formed in the substrate that is substantially coplanar with the substrate than a sidewall surface portion (112) of the at least one recessed feature (102). A portion of the metal seed layer (106) is etched from the top surface portion (114) of the at least one recessed feature (102) to improve coverage of the metal seed layer (106) along the sidewall surface portion (112) of the at least one recessed feature (102) and to mitigate overhang of the metal seed layer.

Abstract: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

Abstract: The present invention provides a capacitor [205]. The capacitor [205] includes a first conductive layer [206] located on an interconnect structure [226] formed in a dielectric layer [228], a capacitor dielectric layer [208] located over the first conductive layer [206] and a second conductive layer [210] located over the capacitor dielectric layer [208]. The recess relief in the surface of the dielectric layer [228] attributable to a fabrication process has been reduced about the interconnect structure [226] to provide a more planar deposition surface over which the capacitor's [205] layers may be deposited.

Abstract: A process of removing fluorine from a chemical deposition reactor includes the step of injecting a gaseous mixture of nitrogen and hydrogen into the reactor, the volume ratio of nitrogen to hydrogen in the gaseous mixture being in the range of from 1:1 to 6:1. More preferably the N2/H2 ratio is in the range of 2.5 to 4.5:1. The gaseous mixture is ionized with a RF induced energy discharge, with a RF power setting typically in the range of from 200 to 250 watts at an RF frequency of 13.5 MHZ. The gaseous mixture is injected into the reactor for a predetermined period of time based upon the thickness of a material, typically a metal such as tungsten, deposited upon a wafer in the reactor during a semiconductor fabrication process.