Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.

Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.

Abstract: Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract: A method of forming an integrated circuit includes forming ?1 hard mask layer on a device layer on a BOX layer of a SOI substrate. A patterned masking layer is used for a trench etch to simultaneously form larger and smaller area trenches through the hard mask layer, device layer and the BOX layer. A dielectric liner is formed for lining the larger and smaller area trenches. A dielectric layer is deposited for completely filling the smaller area trenches and only partially filling the larger area trenches. The larger area trenches are bottom etched through the dielectric layer to provide a top side contact to the handle portion. The handle portion at a bottom of the larger area trenches is implanted to form a handle contact, and the larger area trenches are completely filled with an electrically conductive layer to form a top side ohmic contact to the handle contact.

Abstract: A method of forming an integrated circuit includes forming at least one hard mask layer on a device layer of a silicon-on-Insulator (SOI) substrate. A patterned trench etch forms larger area and smaller area trenches through the hard mask layer, device layer and BOX layer. A dielectric liner is formed for lining the larger area and smaller area trenches. A sub-atmospheric pressure chemical vapor (SACVD) dielectric layer is deposited for filing the smaller area trenches and partially filling the larger area trenches. The larger area trenches are bottom etched through the SACVD layer to provide a through-substrate contact (TSC) to the handle portion. The SACVD layer is densified after bottom etching, the handle portion at a bottom of the larger area trenches is implanted to form a handle contact, and the larger area trenches are filled with an electrically conductive layer to form a top side ohmic contact.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a room mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A microelectronic device with a ferroelectric layer is formed using an MOCVD tool. A substrate is disposed on a susceptor heated to 600° C. to 650° C. A first carrier gas is flowed into a manifold to combine with a plurality of metal organic precursors. The first carrier gas, the metal organic precursors, and a second carrier gas, are flowed through a vaporizer into a chamber of the MOCVD tool, over the substrate. A ratio of a flow rate of the first carrier gas to a flow rate of the metal organic precursors is 250 sccm/milliliter/minute to 500 sccm/milliliter/minute. A ratio of a flow rate of the second carrier gas to a flow rate of the metal organic precursors is 700 sccm/milliliter/minute to 1500 sccm/milliliter/minute. An oxidizing gas is flowed into the chamber over the substrate. The metal organic precursors and the oxidizing gas react to form the ferroelectric layer.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract: A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

Abstract: Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.