Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: A system, method, and computer program product for booting a device are provided herein. The method includes the steps of synchronizing the device based on a downstream signal from a second device, receiving a software from the second device for booting on a reserved downstream channel of the second device, and storing the received first software in a volatile memory. The device does not pre-store the software in a non-volatile memory.

Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: A method for deep-packet inspection of packets flowing through an end unit in a point-to-multipoint network. The method comprises classifying packet flows through the end unit using their flow-identification (ID) to determine which of the packet flows should be deep-packet inspected, wherein the packet flows include incoming packets received from a central unit and outgoing packets sent to the central unit of the point-to-multipoint network; duplicating packets determined to be deep-packet inspected; saving all duplicated packets in a memory; upon collection of a predefined number of duplicated packets belonging to a certain flow-ID, performing deep-packet processing based on at least one deep-packet inspection application; and saving the deep-packet processing results in the memory.

Abstract: A system, method, and computer program product for booting a device are provided herein. The method includes the steps of synchronizing the device based on a downstream signal from a second device, receiving a software from the second device for booting on a reserved downstream channel of the second device, and storing the received first software in a volatile memory. The device does not pre-store the software in a non-volatile memory.

Abstract: Systems and methods are provided for generating an accurate, stable measurement for a laser bias current. The average current and the extinction ratio are controlled using a dual control loop. The transfer function between the laser and a monitor photo diode (MPD) is characterized. A laser driver control module predicts the average power that will be measured using the MPD relative to the data being transmitted, and this information is used to control a laser driver.

Abstract: A method for enabling alternating current (AC) coupling of high-speed burst data signals transmitted by an optical network unit (ONU). The method comprises generating a first data pattern to be sent to an optical transceiver through an AC coupling circuit, wherein the first data pattern is a direct current (DC) balanced pattern; generating a second data pattern to be sent to the optical transceiver through the AC coupling circuit, wherein the second data pattern is output prior to transmission of a high-speed burst data signal; and generating a third data pattern to be sent to the optical transceiver through the AC coupling circuit, wherein the third data pattern is output posterior to the transmission of the high-speed burst data signal.

Abstract: A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.

Abstract: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization unit is clocked by a low frequency clock.

Abstract: A method for deep-packet inspection of packets flowing through an end unit in a point-to-multipoint network. The method comprises classifying packet flows through the end unit using their flow-identification (ID) to determine which of the packet flows should be deep-packet inspected, wherein the packet flows include incoming packets received from a central unit and outgoing packets sent to the central unit of the point-to-multipoint network; duplicating packets determined to be deep-packet inspected; saving all duplicated packets in a memory; upon collection of a predefined number of duplicated packets belonging to a certain flow-ID, performing deep-packet processing based on at least one deep-packet inspection application; and saving the deep-packet processing results in the memory.

Abstract: A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.

Abstract: A method for enabling alternating current (AC) coupling of high-speed burst data signals transmitted by an optical network unit (ONU). The method comprises generating a first data pattern to be sent to an optical transceiver through an AC coupling circuit, wherein the first data pattern is a direct current (DC) balanced pattern; generating a second data pattern to be sent to the optical transceiver through the AC coupling circuit, wherein the second data pattern is output prior to transmission of a high-speed burst data signal; and generating a third data pattern to be sent to the optical transceiver through the AC coupling circuit, wherein the third data pattern is output posterior to the transmission of the high-speed burst data signal.

Abstract: A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.

Abstract: A method for multicasting packets in a passive optical network (PON) residential gateway. The method comprises storing a payload portion of an input packet in a memory; duplicating a header of the input packet to create duplicate headers as the number of destination end-point devices; modifying each of the duplicated header to uniquely designate an output interface of an Ethernet medium access (MAC) adapter coupled to at least one of the destination endpoint devices; passing to the Ethernet MAC adapter its respective modified header together with a pointer to a location of the payload portion in the memory; generating a multicast packet by retrieving the payload portion from the memory and attaching the modified header to the payload portion; and transmitting the multicast packet to the destination endpoint device coupled to the Ethernet MAC adapter.

Abstract: A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.

Abstract: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization module is clocked by a low frequency clock.

Abstract: A gigabit passive optical network (GPON) residential gateway comprising a microprocessor for at least processing packets including voice data and packets including video data; dual packet processors for performing GPON and residential gateway processing tasks; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices; a GPON MAC adapter for interfacing with an optical line terminal (OLT) of the GPON; and a digital signal processor (DSP) for processing voice signals.

Abstract: A gigabit passive optical network (GPON) residential gateway comprising a microprocessor for at least processing packets including voice data and packets including video data; dual packet processors for performing GPON and residential gateway processing tasks; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices; a GPON MAC adapter for interfacing with an optical line terminal (OLT) of the GPON; and a digital signal processor (DSP) for processing voice signals.

Abstract: A method for multicasting packets in a passive optical network (PON) residential gateway. The method comprises storing a payload portion of an input packet in a memory; duplicating a header of the input packet to create duplicate headers as the number of destination end-point devices; modifying each of the duplicated header to uniquely designate an output interface of an Ethernet medium access (MAC) adapter coupled to at least one of the destination endpoint devices; passing to the Ethernet MAC adapter its respective modified header together with a pointer to a location of the payload portion in the memory; generating a multicast packet by retrieving the payload portion from the memory and attaching the modified header to the payload portion; and transmitting the multicast packet to the destination endpoint device coupled to the Ethernet MAC adapter.

Abstract: A system and method for evaluating instances of authorization authority or segregation of duties in an organization against criteria for such authorizations, storing results of such evaluations and presenting such results to a user through queries of the stored results.