Abstract: Hardware acceleration may be leveraged for performing secondary analysis. The hardware acceleration may be implemented by utilizing a plurality of field programmable gate arrays (FPGAs) installed on a device. Requests may be made from client processes for performing secondary analysis of sequencing data at a computing device. Each FPGA may be configured with an engine, or set of engines, configured to perform the secondary analysis to service the requests from client process. An FPGA may be configured with a plurality of engines configured for performing secondary analysis. The FPGA may be configured with a single instance comprising different types of engines for performing different types of secondary analysis. The FPGA may be configured with multiple instances of an engine, or set of engines, configured to perform the same or similar type of secondary analysis. The FPGA may share its resources with multiple client processes using one or more shared engines.