Patents by Inventor Asao Kosakai

Asao Kosakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6344839
    Abstract: In a subfield drive method, two subframes of the least brightness are arranged adjacently to each other to select and light up the display device in terms of the change in image brightness in the time axial direction. When, for example, the level of original signal changes from 7 to 8 or from 8 to 7, SF3, SF2, SF1 and SF1 are selected as subframes for level 8, and SF3, F2 and SF1 are selected as subframes for level 7. This prohibiting any continuous lighting or non-lighting at the levels 7 and 8, there is no substantial change in brightness nor degradation of picture quality at that time. Any distortion of moving image (pseudo contour) is removed by the correction circuit 20 having the frame memory 24 that delays by one frame, the correction constant set circuit 26 that outputs correction data, and the adder 28 that adds the correction data to the original image signal.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: February 5, 2002
    Assignee: Fujitsu General Limited
    Inventors: Hayato Denda, Masamichi Nakajima, Asao Kosakai, Junichi Onodera, Masayuki Kobayashi, Seiji Matsunaga
  • Patent number: 6069610
    Abstract: In an error diffusion processing unit to get a false half tone diffusing in the surroundings the luminance error between the original picture element signal quantizedly input and the preceding data, one dot of said signal is converted into plural picture elements. The respective picture elements (pixels) thus converted are compared with the prior data to detect the luminance error, which will then be weighted by multiplying it with certain coefficient to give, for instance, the reproduced error in one line past, that in one dot past and further the reproduced error a in one-line and one-dot past, which will respectively be added to the original pixels. Producing a false tone by error variance in unit of pixel enables to display the half tone without expanding the half tone display area beyond required dot number.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: May 30, 2000
    Assignee: Fujitsu General Limited
    Inventors: Hayato Denda, Masamichi Nakajima, Asao Kosakai, Junichi Onodera, Masayuki Kobayashi, Seiji Matsunaga
  • Patent number: 6061040
    Abstract: In a display device in which each group of plural drive elements takes charge of the drive of plural picture elements (pixels) and the display luminance changes as the number of sustaining pulses changes that are supplied to a plasma display panel, a constant emission luminance characteristic is maintained by increasing the number of sustaining pulses for a larger load when the display load factor is large, and decreasing the number of sustaining pulses for a smaller load when the display load factor is small. When displaying a multi-tone image by a subfield drive method, a display area detect circuit allows the display of an image with constant luminance characteristic despite the variation of the display load factor, and prevents the deterioration of tone characteristic due to the subfield drive method, and further, a half tone display circuit allows the decrease of the bit number thereby simplifying the configuration of the display area detect circuit.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: May 9, 2000
    Assignee: Fujitsu General Limited
    Inventors: Junichi Onodera, Masamichi Nakajima, Asao Kosakai, Masayuki Kobayashi, Hayato Denda, Seiji Matsunaga, Toru Aida
  • Patent number: 5790095
    Abstract: Coupled to an error variance circuit 11 is an emission luminance characteristic acquisition circuit 20 that counts up, at a display number counter 21, the display number in the single or plural frames of the respective bits of image data by the counters, M in number, corresponding to said bits, then solves for display area percentage (Sk) dividing, at a display area percentage operation part 22, the display dot number as counted at a display number counter 21, by total dot number, and acquires the luminance deviation characteristic for each bit by means of an emission luminance deviation characteristic measuring part 24. The luminance deviation thus obtained is renewed for each frame and transferred to the error variance circuit 11, and processed for error variance on the basis of the emission luminance characteristic to be output at PDP.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: August 4, 1998
    Assignee: Fujitsu General Limited
    Inventors: Junichi Onodera, Masamichi Nakajima, Asao Kosakai, Masayuki Kobayashi, Hayato Denda, Seiji Matsunaga
  • Patent number: 5760756
    Abstract: An error variance circuit, wherein a reproduced error, as detected at an error detection circuit, is added to the image signal of the input signal picture element of n bits, and wherein a variance output signal is converted into a signal of m (.ltoreq.n-l) bits and outputted to a display panel, includes a clear circuit that clears error at each frame and forcibly reduces the prior error to zero thus preventing excessive noise from preceding frames and non-image duration causing flickering of picture.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: June 2, 1998
    Assignee: Fujitsu General Limited
    Inventors: Masayuki Kobayashi, Masamichi Nakajima, Asao Kosakai, Junichi Onodera, Hayato Denda