Patents by Inventor Asayoshi Kawashita

Asayoshi Kawashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5564033
    Abstract: An external memory unit for a data processing system has a plurality of detachable memory media. Data is written in parallel to the memory media. Since the positions of the memory media can be switched, reference information is written in each of the media during an initialization process. Once initialized, the data can be read from and written to the memory media regardless of their current and former positions in the external memory unit. The reference information has sequence information indicating the position of a memory medium in a sequence when data is first written to a group of media as part of an operation that subdivides data and writes the subunits to the group. The name of the group is also included in the reference information. When a subsequent read or write operation is requested, the group information is used to determine if all of the media required for executing the request are present in the external memory unit, and if so, the operation is executed.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: October 8, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Toshitsugu Takekuma, Shozo Satake, Asayoshi Kawashita
  • Patent number: 5283790
    Abstract: An external storage apparatus which includes a recording medium on which a replacing area or defective spare block area is used in place of a defective block. Reassignment processing of the replacing area to the defective block is performed under a command issued by a host system. A managing unit manages the number of blocks remaining unused in the replacing area. Upon reception of the command for assigning the replacing area to the defective block from the host system, the reassignment processing of the defective block from the host system, the reassignment processing of the defective block is performed, and the number of blocks remaining in the replacing area which is managed by the managing unit is supplied to the host system.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: February 1, 1994
    Assignee: Hitachi, Ltd.
    Inventor: Asayoshi Kawashita
  • Patent number: 5070417
    Abstract: A disc drive control method in which a command for disc rotation is sent to the disc drive mechanism upon receipt of a `drive-ON` signal, a timing operation is started in response to receipt of a `drive-OFF` signal, and a command for stoppage of the disc rotation is sent to the disc drive mechanism if there is no further `drive-ON` signal received within a predetermined time interval. A disc drive control system comprises devices for effecting the steps of the disc drive control method. A disc drive unit employable in the disc drive control method and system comprises a disc drive mechanism for producing rotational movement of a disc and a disc drive control device for controlling rotation of the disc by means of the disc drive mechanism. The disc drive control method and/or system may also be applied to an information processing system which comprises at least a processor and a flexible disc drive unit.
    Type: Grant
    Filed: November 21, 1989
    Date of Patent: December 3, 1991
    Assignee: Hitachi, Ltd.
    Inventor: Asayoshi Kawashita
  • Patent number: 4648132
    Abstract: In a communication system for performing the transmission and reception of data among a plurality of equipment, a communication control apparatus for governing the transmission and reception of data is connected to each of the equipment.
    Type: Grant
    Filed: July 18, 1983
    Date of Patent: March 3, 1987
    Assignee: Hitachi, Ltd.
    Inventor: Asayoshi Kawashita
  • Patent number: 4631671
    Abstract: A data processing system having a data bus with a two-byte capacity provides for the DMA transfer of both one-byte data and two-byte data between a memory and an input/output adapter. An address counter and a byte counter receive a start address and a byte number indicating the number of bytes to be transferred, respectively, through the system bus from the processor. The least significant bits in the start address and the byte number are used to control whether the data transfer on the bus will be a one-byte transfer or a two-byte transfer for the first transfer operation and the last transfer operation.
    Type: Grant
    Filed: November 23, 1982
    Date of Patent: December 23, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Asayoshi Kawashita, Hirofumi Kuniga