Patents by Inventor Aseem Maheshwari

Aseem Maheshwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method to provide non-coherent access to a coherent memory system
    Patent number: 9569366
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: February 14, 2017
    Assignee: Cavium, Inc.
    Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
  • Processor with efficient work queuing
    Patent number: 9465662
    Abstract: Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: October 11, 2016
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, Aseem Maheshwari, Robert Sanzone
  • DRAM address protection
    Patent number: 9239753
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 19, 2016
    Assignee: Cavium, Inc.
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler
  • DRAM ADDRESS PROTECTION
    Publication number: 20150169399
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler
  • DRAM address protection
    Patent number: 8977944
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Cavium, Inc.
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler
  • System and Method to Provide Non-Coherent Access to a Coherent Memory System
    Publication number: 20140372709
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 18, 2014
    Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
  • System and method to provide non-coherent access to a coherent memory system
    Patent number: 8850125
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 30, 2014
    Assignee: Cavium, Inc.
    Inventors: Jeffrey Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
  • SYSTEM AND METHOD TO PROVIDE NON-COHERENT ACCESS TO A COHERENT MEMORY SYSTEM
    Publication number: 20130103909
    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Cavium, Inc.
    Inventors: Jeffrey Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
  • Processor With Efficient Work Queuing
    Publication number: 20130097608
    Abstract: Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 18, 2013
    Applicant: Cavium, Inc.
    Inventors: Richard E. Kessler, Aseem Maheshwari, Robert Sanzone
  • DRAM ADDRESS PROTECTION
    Publication number: 20120185752
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Application
    Filed: December 14, 2011
    Publication date: July 19, 2012
    Applicant: Cavium, Inc.
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler