Patents by Inventor Asen Asenov
Asen Asenov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757002Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.Type: GrantFiled: May 4, 2021Date of Patent: September 12, 2023Assignee: SemiWise LimitedInventor: Asen Asenov
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Publication number: 20230171944Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. A first region is in electrical contact with the floating body region. A second region is in electrical contact with the floating body region and is spaced apart from the first region. A gate is positioned between the first and second regions. A buried layer is provided beneath the floating body region. An insulating layer is configured to insulate the memory cell from adjacent memory cells in a first direction. A buried insulating layer is configured to insulate the memory cell from adjacent memory cells in a second direction perpendicular to the first direction.Type: ApplicationFiled: May 25, 2021Publication date: June 1, 2023Inventors: Asen Asenov, Valerii Nebesnyi, Yuniarto Widjaja, Jin-Woo Han, Tapas Dutta, Fikru Adamu-Lema
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Publication number: 20210257456Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.Type: ApplicationFiled: May 4, 2021Publication date: August 19, 2021Inventor: Asen Asenov
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Patent number: 11049939Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.Type: GrantFiled: August 2, 2016Date of Patent: June 29, 2021Assignee: SemiWise LimitedInventor: Asen Asenov
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Patent number: 10740525Abstract: A method for simulating semiconductor devices includes running ensemble Monte Carlo (EMC) simulations of a plurality of semiconductor devices having a first plurality of configurations in a Design of Experiment (DoE) space to produce EMC results. Mobility parameters are extracted across the DoE space from the EMC results. A response-surface mobility model is constructed using the extracted mobility parameters. The response-surface mobility model is used to run a drift-diffusion simulation of a semiconductor device with a different configuration from the first plurality of configurations.Type: GrantFiled: May 9, 2016Date of Patent: August 11, 2020Assignee: SYNOPSYS, INC.Inventor: Asen Asenov
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Patent number: 9922713Abstract: Provided is an electronic device, such as a flash memory device and/or a write-once-read-once memory device, where the device has a polyoxometallate that is capable of providing and/or accepting one or more electrons. The polyoxometallate may have a Wells-Dawson structure and the polyoxometallate may comprise a cage and optionally one or more guests. Also provided is a method of using the memory device, the method comprising the step of providing to or accepting from the polyoxometalate one or more electrons to provide a polyoxometalate in a reduced or oxidized state.Type: GrantFiled: October 30, 2014Date of Patent: March 20, 2018Assignee: The University Court of the University of GlasgowInventors: Leroy Cronin, Asen Asenov
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Patent number: 9847404Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.Type: GrantFiled: September 11, 2013Date of Patent: December 19, 2017Assignees: SemiWise Limited, Semi Solutions LLCInventors: Robert J. Strain, Asen Asenov
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Publication number: 20170103153Abstract: In one embodiment, a method for simulating semiconductor devices includes the steps: running ensemble Monte Carlo (EMC) simulations of a plurality of semiconductor devices having a first plurality of configurations in a Design of Experiment (DoE) space to produce EMC results; extracting mobility parameters across the DoE space from the EMC results; constructing a response-surface mobility model using the extracted mobility parameters; and using the response-surface mobility model to run a drift-diffusion simulation of a semiconductor device with a different configuration from the first plurality of configurations.Type: ApplicationFiled: May 9, 2016Publication date: April 13, 2017Inventor: Asen ASENOV
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Publication number: 20170040449Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.Type: ApplicationFiled: August 2, 2016Publication date: February 9, 2017Inventor: Asen Asenov
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Publication number: 20160254058Abstract: Provided is an electronic device, such as a flash memory device and/or a write-once-read-once memory device, where the device has a polyoxometallate that is capable of providing and/or accepting one or more electrons. The polyoxometallate may have a Wells-Dawson structure and the polyoxometallate may comprise a cage and optionally one or more guests. Also provided is a method of using the memory device, the method comprising the step of providing to or accepting from the polyoxometalate one or more electrons to provide a polyoxometalate in a reduced or oxidised state.Type: ApplicationFiled: October 30, 2014Publication date: September 1, 2016Inventors: Leroy CRONIN, Asen ASENOV
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Patent number: 9373684Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.Type: GrantFiled: March 20, 2012Date of Patent: June 21, 2016Assignee: SemiWise LimitedInventors: Asen Asenov, Gareth Roy
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Patent number: 9312362Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.Type: GrantFiled: March 20, 2015Date of Patent: April 12, 2016Assignee: SemiWise LimitedInventors: Asen Asenov, Gareth Roy
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Patent number: 9269804Abstract: The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.Type: GrantFiled: July 25, 2013Date of Patent: February 23, 2016Assignee: SemiWise LimitedInventor: Asen Asenov
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Patent number: 9263568Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional ?-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.Type: GrantFiled: July 25, 2013Date of Patent: February 16, 2016Assignee: SemiWise LimitedInventor: Asen Asenov
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Patent number: 9190485Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.Type: GrantFiled: July 25, 2013Date of Patent: November 17, 2015Assignee: Gold Standard Simulations Ltd.Inventor: Asen Asenov
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Publication number: 20150194505Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.Type: ApplicationFiled: March 20, 2015Publication date: July 9, 2015Inventors: Asen Asenov, Gareth Roy
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Patent number: 9012276Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.Type: GrantFiled: July 3, 2014Date of Patent: April 21, 2015Assignee: Gold Standard Simulations Ltd.Inventors: Ashok K. Kapoor, Asen Asenov
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Patent number: 8994123Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.Type: GrantFiled: March 20, 2012Date of Patent: March 31, 2015Assignee: Gold Standard Simulations Ltd.Inventors: Asen Asenov, Gareth Roy
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Publication number: 20150011056Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.Type: ApplicationFiled: July 3, 2014Publication date: January 8, 2015Inventors: Ashok K. Kapoor, Asen Asenov
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Publication number: 20150008490Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.Type: ApplicationFiled: September 11, 2013Publication date: January 8, 2015Applicants: SEMI SOLUTIONS LLC, GOLD STANDARD SIMULATIONS LTD.Inventors: Robert J. Strain, Asen Asenov