Patents by Inventor Asen Asenov

Asen Asenov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210257456
    Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventor: Asen Asenov
  • Patent number: 11049939
    Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 29, 2021
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Patent number: 10740525
    Abstract: A method for simulating semiconductor devices includes running ensemble Monte Carlo (EMC) simulations of a plurality of semiconductor devices having a first plurality of configurations in a Design of Experiment (DoE) space to produce EMC results. Mobility parameters are extracted across the DoE space from the EMC results. A response-surface mobility model is constructed using the extracted mobility parameters. The response-surface mobility model is used to run a drift-diffusion simulation of a semiconductor device with a different configuration from the first plurality of configurations.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 11, 2020
    Assignee: SYNOPSYS, INC.
    Inventor: Asen Asenov
  • Patent number: 9922713
    Abstract: Provided is an electronic device, such as a flash memory device and/or a write-once-read-once memory device, where the device has a polyoxometallate that is capable of providing and/or accepting one or more electrons. The polyoxometallate may have a Wells-Dawson structure and the polyoxometallate may comprise a cage and optionally one or more guests. Also provided is a method of using the memory device, the method comprising the step of providing to or accepting from the polyoxometalate one or more electrons to provide a polyoxometalate in a reduced or oxidized state.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 20, 2018
    Assignee: The University Court of the University of Glasgow
    Inventors: Leroy Cronin, Asen Asenov
  • Patent number: 9847404
    Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 19, 2017
    Assignees: SemiWise Limited, Semi Solutions LLC
    Inventors: Robert J. Strain, Asen Asenov
  • Publication number: 20170103153
    Abstract: In one embodiment, a method for simulating semiconductor devices includes the steps: running ensemble Monte Carlo (EMC) simulations of a plurality of semiconductor devices having a first plurality of configurations in a Design of Experiment (DoE) space to produce EMC results; extracting mobility parameters across the DoE space from the EMC results; constructing a response-surface mobility model using the extracted mobility parameters; and using the response-surface mobility model to run a drift-diffusion simulation of a semiconductor device with a different configuration from the first plurality of configurations.
    Type: Application
    Filed: May 9, 2016
    Publication date: April 13, 2017
    Inventor: Asen ASENOV
  • Publication number: 20170040449
    Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 9, 2017
    Inventor: Asen Asenov
  • Publication number: 20160254058
    Abstract: Provided is an electronic device, such as a flash memory device and/or a write-once-read-once memory device, where the device has a polyoxometallate that is capable of providing and/or accepting one or more electrons. The polyoxometallate may have a Wells-Dawson structure and the polyoxometallate may comprise a cage and optionally one or more guests. Also provided is a method of using the memory device, the method comprising the step of providing to or accepting from the polyoxometalate one or more electrons to provide a polyoxometalate in a reduced or oxidised state.
    Type: Application
    Filed: October 30, 2014
    Publication date: September 1, 2016
    Inventors: Leroy CRONIN, Asen ASENOV
  • Patent number: 9373684
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: June 21, 2016
    Assignee: SemiWise Limited
    Inventors: Asen Asenov, Gareth Roy
  • Patent number: 9312362
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 12, 2016
    Assignee: SemiWise Limited
    Inventors: Asen Asenov, Gareth Roy
  • Patent number: 9269804
    Abstract: The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 23, 2016
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Patent number: 9263568
    Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional ?-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 16, 2016
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Patent number: 9190485
    Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: November 17, 2015
    Assignee: Gold Standard Simulations Ltd.
    Inventor: Asen Asenov
  • Publication number: 20150194505
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.
    Type: Application
    Filed: March 20, 2015
    Publication date: July 9, 2015
    Inventors: Asen Asenov, Gareth Roy
  • Patent number: 9012276
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 21, 2015
    Assignee: Gold Standard Simulations Ltd.
    Inventors: Ashok K. Kapoor, Asen Asenov
  • Patent number: 8994123
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Gold Standard Simulations Ltd.
    Inventors: Asen Asenov, Gareth Roy
  • Publication number: 20150008490
    Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.
    Type: Application
    Filed: September 11, 2013
    Publication date: January 8, 2015
    Applicants: SEMI SOLUTIONS LLC, GOLD STANDARD SIMULATIONS LTD.
    Inventors: Robert J. Strain, Asen Asenov
  • Publication number: 20150011056
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 8, 2015
    Inventors: Ashok K. Kapoor, Asen Asenov
  • Publication number: 20140027853
    Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional ?-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 30, 2014
    Applicant: GOLD STANDARD SIMULATIONS LTD.
    Inventor: Asen Asenov
  • Publication number: 20140027854
    Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 30, 2014
    Applicant: Gold Standard Simulations Ltd.
    Inventor: Asen Asenov