Abstract: A method for transmitting data between the inside and outside of a hermetically sealed chamber, including: serializing first data into a first serial data for transmission; transmitting the first serial data at a first frequency using a first transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the first transmission line is coupled to a first ground.

Abstract: A method for transmitting data between the inside and outside of a hermetically sealed chamber, including: serializing first data into a first serial data for transmission; transmitting the first serial data at a first frequency using a first transmission line that connects the inside and outside of the hermetically sealed chamber; wherein the first transmission line is coupled to a first ground.

Abstract: A method for simultaneous time delay integration (TDI) imaging using multiple channels of a multi-tap device, including: translating a field of view (FOV) over a sample to be imaged; optically aligning a direction of travel of the FOV to a direction of charge transfer for each tap of the multi-tap device; and reading out the image data from each channel using settings that are appropriate to a particular application.

Abstract: A method for operating a focal plane array in a Time Delay Integration (TDI) mode, the method including: shifting a number of rows during TDI integration, wherein the number of rows shifted is less than a total number of rows of the focal plane array; and reading out a number of rows equal to the total number of rows of the focal plane array minus the number of rows shifted, leaving behind the partially-integrated rows.

Abstract: A method for operating a focal plane array in a Time Delay Integration (TDI) mode, the method including: shifting a number of rows during TDI integration, wherein the number of rows shifted is less than a total number of rows of the focal plane array; and reading out a number of rows equal to the total number of rows of the focal plane array minus the number of rows shifted, leaving behind the partially-integrated rows.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.