Patents by Inventor Ashan WICKRAMASINGHE

Ashan WICKRAMASINGHE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Unified power format annotated RTL image recognition to accelerate low power verification convergence
    Patent number: 12353810
    Abstract: A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design with another combined feature array, and reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 8, 2025
    Assignee: Synopsys, Inc.
    Inventors: Zamrath Nizam, Chirath Chamikara Diyagama, Bhaskar Pal, Ashan Wickramasinghe
  • UNIFIED POWER FORMAT ANNOTATED RTL IMAGE RECOGNITION TO ACCELERATE LOW POWER VERIFICATION CONVERGENCE
    Publication number: 20230043751
    Abstract: A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design with another combined feature array, and reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.
    Type: Application
    Filed: July 19, 2022
    Publication date: February 9, 2023
    Applicant: Synopsys, Inc.
    Inventors: Zamrath NIZAM, Chirath Chamikara DIYAGAMA, Bhaskar PAL, Ashan WICKRAMASINGHE