Patents by Inventor Ashay Chitnis
Ashay Chitnis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10873002Abstract: A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by deposition or as a preform. The invention provides a low cost, simple and reliable wafer bonding technology which can be used in a variety of device fabrication processes, including flip chip packaging.Type: GrantFiled: October 20, 2006Date of Patent: December 22, 2020Assignee: Cree, Inc.Inventor: Ashay Chitnis
-
Patent number: 10211296Abstract: An epitaxial group-III-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-III-nitride layers, wherein the interlayer structure comprises a group-III-nitride interlayer material having a larger band gap than the materials of the first and second group-III-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-III-nitride layers.Type: GrantFiled: July 3, 2018Date of Patent: February 19, 2019Assignee: AzurSpace Solar Power GmbHInventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
-
Patent number: 10199360Abstract: A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.Type: GrantFiled: March 3, 2017Date of Patent: February 5, 2019Assignee: Cree, Inc.Inventors: Bernd Keller, Ashay Chitnis, Nicholas W. Medendorp, Jr., James Ibbetson, Max Batres
-
Publication number: 20180331187Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Applicant: AZURSPACE Solar Power GmbHInventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
-
Patent number: 10026814Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: GrantFiled: September 11, 2017Date of Patent: July 17, 2018Assignee: AZURSPACE Solar Power GmbHInventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
-
Publication number: 20170373156Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: ApplicationFiled: September 11, 2017Publication date: December 28, 2017Applicant: AZURSPACE Solar Power GmbHInventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
-
Patent number: 9786744Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: GrantFiled: November 2, 2016Date of Patent: October 10, 2017Assignee: AZURSPACE Solar Power GmbHInventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
-
Publication number: 20170179088Abstract: A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: Bernd Keller, Ashay Chitnis, Nicholas W. Medendorp, JR., James Ibbetson, Max Batres
-
Patent number: 9634191Abstract: A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.Type: GrantFiled: November 14, 2007Date of Patent: April 25, 2017Assignee: CREE, INC.Inventors: Bernd Keller, Ashay Chitnis, Nicholas W. Medendorp, Jr., James Ibbetson, Max Batres
-
Publication number: 20170077242Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: ApplicationFiled: November 2, 2016Publication date: March 16, 2017Applicant: AZURSPACE Solar Power GmbHInventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
-
Patent number: 9496349Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: GrantFiled: August 17, 2015Date of Patent: November 15, 2016Assignee: AZURSPACE Solar Power GmbHInventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
-
Patent number: 9368428Abstract: A method for fabricating semiconductor and electronic devices at the wafer level is described. In this method, dielectric material is used to wafer bond a device wafer to a submount wafer, after which vias can be structured into the submount wafer and dielectric bonding material to access contact pads on the bonded surface of the device wafer. The vias may subsequently be filled with electrically and thermally conducting material to provide electrical contacts to the device and improve the thermal properties of the finished device, respectively. The post-bonding process described provides a method for fabricating a variety of electronic and semiconductor devices, particularly light emitting diodes with electrical contacts at the bottom of the chip.Type: GrantFiled: April 3, 2007Date of Patent: June 14, 2016Assignee: CREE, INC.Inventors: Ashay Chitnis, James Ibbetson
-
Publication number: 20150357419Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Applicant: AZURSPACE SOLAR POWER GMBHInventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
-
Patent number: 9196799Abstract: Methods for fabricating semiconductor devices such as LED chips at the wafer level, and LED chips and LED chip wafers fabricated using the methods. An LED chip wafer according to the present invention comprises a plurality of LEDs on a wafer and a plurality of pedestals, each of which is on one of the LEDs. A fluorescent substrate or preform (“preform”) is provided covering at least some of the LEDs, the preform comprising holes with the pedestals arranged within the holes. During operation of the covered ones of said LEDs at least some light from the LEDs passes through the preform and is converted. LED chips are provided that are singulated from this LED chip wafer. One embodiment of a method for fabricating LED chips from a wafer comprises depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. Pedestals are formed on the LEDs and a fluorescent preform is formed with holes.Type: GrantFiled: August 22, 2008Date of Patent: November 24, 2015Assignee: Cree, Inc.Inventors: Ashay Chitnis, Bernd Keller
-
Patent number: 9159888Abstract: Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.Type: GrantFiled: September 7, 2007Date of Patent: October 13, 2015Assignee: Cree, Inc.Inventors: Ashay Chitnis, James Ibbetson, Bernd Keller, David T. Emerson, John Edmond, Michael J. Bergmann, Jasper S. Cabalu, Jeffrey C. Britt, Arpan Chakraborty, Eric Tarsa, Yankun Fu
-
Patent number: 9024349Abstract: Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.Type: GrantFiled: January 22, 2007Date of Patent: May 5, 2015Assignee: Cree, Inc.Inventors: Ashay Chitnis, James Ibbetson, Arpan Chakraborty, Eric J. Tarsa, Bernd Keller, James Seruto, Yankun Fu
-
Publication number: 20150008457Abstract: Methods for fabricating light emitting diode (LED) chips one of which comprises flip-chip mounting a plurality of LEDs on a surface of a submount wafer and forming a coating over said LEDs. The coating comprising a conversion material at least partially covering the LEDs. The coating is planarized to the desired thickness with the coating being continuous and unobstructed on the top surface of the LEDs. The LEDs chips are then singulated from the submount wafer. An LED chip comprising a lateral geometry LED having first and second contacts, with the LED flip-chip mounted to a submount by a conductive bonding material. A phosphor loaded binder coats and at least partially covers the LED. The binder provides a substantially continuous and unobstructed coating over the LED. The phosphor within the coating absorbs and converts the wavelength of at least some of the LED light with the coating planarized to achieve the desired emission color point of the LED chip.Type: ApplicationFiled: September 24, 2014Publication date: January 8, 2015Inventors: Ashay Chitnis, James Ibbetson, Bernd Keller
-
Patent number: 8878219Abstract: Methods for fabricating light emitting diode (LED) chips one of which comprises flip-chip mounting a plurality of LEDs on a surface of a submount wafer and forming a coating over said LEDs. The coating comprising a conversion material at least partially covering the LEDs. The coating is planarized to the desired thickness with the coating being continuous and unobstructed on the top surface of the LEDs. The LEDs chips are then singulated from the submount wafer. An LED chip comprising a lateral geometry LED having first and second contacts, with the LED flip-chip mounted to a submount by a conductive bonding material. A phosphor loaded binder coats and at least partially covers the LED. The binder provides a substantially continuous and unobstructed coating over the LED. The phosphor within the coating absorbs and converts the wavelength of at least some of the LED light with the coating planarized to achieve the desired emission color point of the LED chip.Type: GrantFiled: January 11, 2008Date of Patent: November 4, 2014Assignee: Cree, Inc.Inventors: Ashay Chitnis, James Ibbetson, Bernd Keller
-
Patent number: 8877524Abstract: A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED chips comprises light from the conversion material, typically in combination with LED light. The emission characteristics of at least some of the LED chips is measured and at least some of the conversion material over the LEDs is removed to alter the emission characteristics of the LED chips. The invention is particularly applicable to fabricating LED chips on a wafer where the LED chips have light emission characteristics that are within a range of target emission characteristics. This target range can fall within an emission region on a CIE curve to reduce the need for binning of the LEDs from the wafer.Type: GrantFiled: March 30, 2009Date of Patent: November 4, 2014Assignee: Cree, Inc.Inventors: Ashay Chitnis, John Edmond, Jeffrey Carl Britt, Bernd P. Keller, David Todd Emerson, Michael John Bergmann, Jasper S. Cabalu
-
Patent number: 8617997Abstract: The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes.Type: GrantFiled: August 21, 2007Date of Patent: December 31, 2013Assignee: Cree, Inc.Inventor: Ashay Chitnis