Patents by Inventor Ashay Narsale
Ashay Narsale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230403237Abstract: According to examples, a system for aligning a plurality of variously encoded content streams is described. The system may include a processor and a memory storing instructions. The processor, when executing the instructions, may cause the system to receive a request to transmit one or more packets of a message over a network, upon receive the request, designate a message sequence number (MSN) for the message, and upon receive the request, designate a packet sequence number (PSN) for one or more packets of the message.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: Meta Platforms, Inc.Inventors: Arvind SRINIVASAN, Nicolaas Johannes Viljoen, Pankaj Kansal, Ashay Narsale
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Patent number: 11741013Abstract: Various embodiments described herein provide for using a prefetch buffer with a cache of a memory sub-system to store prefetched data (e.g., data prefetched from the cache), which can increase read access or sequential read access of the memory sub-system over that of traditional memory sub-systems.Type: GrantFiled: May 19, 2022Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventor: Ashay Narsale
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Patent number: 11599466Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.Type: GrantFiled: March 25, 2022Date of Patent: March 7, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Robert M. Walker, Ashay Narsale
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Publication number: 20220276963Abstract: Various embodiments described herein provide for using a prefetch buffer with a cache of a memory sub-system to store prefetched data (e.g., data prefetched from the cache), which can increase read access or sequential read access of the memory sub-system over that of traditional memory sub-systems.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Inventor: Ashay Narsale
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Publication number: 20220214971Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Robert M. Walker, Ashay Narsale
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Patent number: 11372763Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.Type: GrantFiled: July 14, 2020Date of Patent: June 28, 2022Assignee: Micron Technology, Inc.Inventors: Ashay Narsale, Robert Walker
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Patent number: 11372762Abstract: Various embodiments described herein provide for using a prefetch buffer with a cache of a memory sub-system to store prefetched data (e.g., data prefetched from the cache), which can increase read access or sequential read access of the memory sub-system over that of traditional memory sub-systems.Type: GrantFiled: July 14, 2020Date of Patent: June 28, 2022Assignee: Micron Technology, Inc.Inventor: Ashay Narsale
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Patent number: 11301380Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.Type: GrantFiled: May 18, 2020Date of Patent: April 12, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Robert M. Walker, Ashay Narsale
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Publication number: 20220019536Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Inventors: Ashay Narsale, Robert Walker
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Publication number: 20220019535Abstract: Various embodiments described herein provide for using a prefetch buffer with a cache of a memory sub-system to store prefetched data (e.g., data prefetched from the cache), which can increase read access or sequential read access of the memory sub-system over that of traditional memory sub-systems.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Inventor: Ashay Narsale
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Publication number: 20210357324Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.Type: ApplicationFiled: May 18, 2020Publication date: November 18, 2021Inventors: Robert M. Walker, Ashay Narsale
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Patent number: 10691595Abstract: A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent.Type: GrantFiled: August 21, 2018Date of Patent: June 23, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Robert M. Walker, Ashay Narsale
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Patent number: 10599575Abstract: A method to cache memory requests while accounting for phase change memory cell drift is described. The method includes adding, in response to receiving a write memory request from a host system, an entry to a cache that includes user data of the write memory request, wherein the write memory request is directed to a set of phase change memory cells; adding, in response to receiving the write memory request, an entry in a first content-addressable memory (CAM), wherein the entry in the first CAM includes a reference to the entry in the cache that includes the user data of the write memory request; writing the user data of the write memory request to the set of phase change memory cells; and adding an entry to a second CAM, wherein the entry in the second CAM includes a reference to the entry in the cache that includes the user data.Type: GrantFiled: August 9, 2018Date of Patent: March 24, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Ashay Narsale, Robert M. Walker
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Publication number: 20200065243Abstract: A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Robert M. WALKER, Ashay NARSALE
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Publication number: 20200050549Abstract: A method to cache memory requests while accounting for phase change memory cell drift is described. The method includes adding, in response to receiving a write memory request from a host system, an entry to a cache that includes user data of the write memory request, wherein the write memory request is directed to a set of phase change memory cells; adding, in response to receiving the write memory request, an entry in a first content-addressable memory (CAM), wherein the entry in the first CAM includes a reference to the entry in the cache that includes the user data of the write memory request; writing the user data of the write memory request to the set of phase change memory cells; and adding an entry to a second CAM, wherein the entry in the second CAM includes a reference to the entry in the cache that includes the user data.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Ashay NARSALE, Robert M. WALKER
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Publication number: 20200043551Abstract: A method for caching memory requests while accounting for a phase change memory cell drift phenomenon is described. The method includes writing first user data to an address in phase change memory cells; setting a timer in a set of data structures to a first value in response to writing the first user data to the phase change memory cells, wherein the data structures are stored outside the phase change memory cells; determining whether the timer corresponding to the first user data has expired; and fulfilling a read request for the address from the set of data structures in response to determining that the timer has not expired.Type: ApplicationFiled: August 6, 2018Publication date: February 6, 2020Inventors: Ashay NARSALE, Robert M. WALKER
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Patent number: 10553278Abstract: A method for caching memory requests while accounting for a phase change memory cell drift phenomenon is described. The method includes writing first user data to an address in phase change memory cells; setting a timer in a set of data structures to a first value in response to writing the first user data to the phase change memory cells, wherein the data structures are stored outside the phase change memory cells; determining whether the timer corresponding to the first user data has expired; and fulfilling a read request for the address from the set of data structures in response to determining that the timer has not expired.Type: GrantFiled: August 6, 2018Date of Patent: February 4, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Ashay Narsale, Robert M. Walker