Patents by Inventor Asheesh Bhardwaj

Asheesh Bhardwaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11113062
    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Asheesh Bhardwaj, Timothy David Anderson, Son Hung Tran
  • Publication number: 20200371798
    Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.
    Type: Application
    Filed: May 20, 2020
    Publication date: November 26, 2020
    Inventors: Asheesh Bhardwaj, Mujibur Rahman, Timothy David Anderson
  • Publication number: 20200371793
    Abstract: A method to store source data in a processor in response to a bit-reversed vector store instruction includes specifying, in respective fields of the bit-reversed vector store instruction, a first source register containing the source data and a second source register containing address data. The first source register includes a plurality of lanes and each lane contains an initial data element having an associated index value. The method also includes executing the bit-reversed vector store instruction by creating reordered source data by, for each lane, replacing the initial data element in the lane with the data element having a bit-reversed index value relative to the associated index value of the initial data element; and storing the reordered source data in contiguous locations in a memory beginning at a location specified by the address data.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Asheesh BHARDWAJ, Dheera Balasubramanian SAMUDRALA, Timothy D. ANDERSON
  • Publication number: 20200373913
    Abstract: A method is provided that includes performing, by a processor in response to a vector finite impulse response (VFIR) filter instruction, generating of a plurality of filter outputs using a plurality of coefficients and a plurality of sequential data elements, the plurality of coefficients specified by a coefficient operand of the VFIR filter instruction and the plurality of sequential data elements specified by a data operand of the VFIR filter instruction, and storing the filter outputs in a storage location specified by the VFIR filter instruction.
    Type: Application
    Filed: May 20, 2020
    Publication date: November 26, 2020
    Inventors: Mujibur Rahman, Asheesh Bhardwaj, Timothy David Anderson
  • Patent number: 10809933
    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 20, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur John Redfern, Asheesh Bhardwaj
  • Patent number: 10809978
    Abstract: A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arthur John Redfern, Asheesh Bhardwaj, Tarek Aziz Lahlou, William Franklin Leven
  • Publication number: 20190278597
    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array, a null vector count (N), and a selected dimension. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. N null stream vectors are inserted into the stream of vectors for the selected dimension without fetching respective null data from the memory.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Asheesh Bhardwaj, William Franklin Leven, Son Hung Tran, Timothy David Anderson
  • Publication number: 20190278596
    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: William Franklin Leven, Asheesh Bhardwaj, Son Hung Tran, Timothy David Anderson
  • Publication number: 20190278598
    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Asheesh Bhardwaj, Timothy David Anderson, Son Hung Tran
  • Publication number: 20180349096
    Abstract: A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 6, 2018
    Inventors: Arthur John REDFERN, Asheesh BHARDWAJ, Tarek Aziz LAHLOU, William Franklin LEVEN
  • Patent number: 10114796
    Abstract: An improved biquad infinite impulse response filter is shown that may be implemented in a very large instruction word digital signal processor as well as in other processing circuitry. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Asheesh Bhardwaj, Lester A Longley
  • Publication number: 20180246669
    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 30, 2018
    Inventors: Arthur John Redfern, Asheesh Bhardwaj
  • Publication number: 20160112033
    Abstract: An improved biquad infinite impulse response filter is shown that may be implemented in a very large instruction word digital signal processor as well as in other processing circuitry. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Asheesh Bhardwaj, Lester A. Longley