Abstract: Capabilities and features of a modem are specified in accordance with descriptions of applications to be executed on the modem. The specification of the modem using individual applications enables the verification of intended performance based on the individual applications, simplifying the testing and assuring of the modem. To that end, a method implemented by a cloud computing resource (CCR) includes receiving, by the CCR, a description of an application supported by a modem. A dataflow fragment (DFF) for the application is generated by the CCR and is stored by the CCR in a memory, The DFF is retrieved and provided to the modem based on a description of the modem.

Abstract: A prefetch buffer and prefetch method. In one embodiment, the prefetch buffer has a main buffer embodied as a direct-mapped cache, and the prefetch buffer includes: (1) an alias buffer associated with the main buffer and (2) a prefetch controller associated with the main buffer and the alias buffer and operable to cause the alias buffer to store potentially aliasing cachelines of a loop body instead of the main buffer.

Abstract: A data processing element includes an input unit configured to provide instructions for scalar, vector and array processing, and a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity. Additionally, the data processing element includes a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity. The data processing element further includes an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity. A method of operating a data processing element and a MIMO receiver employing a data processing element are also provided.

Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

Abstract: A nodal computer network comprises a plurality of nodes grouped into different classes. The classes include at least a first class of fully interconnected nodes and a second class of fully interconnected nodes, and the first class includes a source node having an information packet to be communicated to a destination node. The source node is configured to divide the information packet into segments and to disperse the segments among the nodes of the first class. The nodes of the first class are configured to transmit each of said segments directly to the nodes of said second class, wherein the first class is not fully interconnected with the second class.

Abstract: An error correction code method comprises examining a validator of one of a plurality of data in a data stream at a first processing stage and directing the one of the plurality of data through at least one subsequent processing stage to a corrected output if the validator indicates an error. The method also includes directing the one of the plurality of data to the corrected output if the validator does not indicate an error.

Abstract: A system, circuit, and method are presented for adjusting a prefetch rate of a prefetch unit from a first rate to a second rate by determining a probability factor associated with a branch instruction. The circuit and method may determine the probability factor based on a type of disparity associated with the branch instruction. The circuit and method may further be adapted to calculate the second rate based on the probability factor. The ability to adjust the prefetch rate of a prefetch unit advantageously decreases the number of memory transactions, thereby decreasing the power consumption of a processing unit.

Abstract: A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.

Abstract: A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.

Abstract: A nodal computer network comprises a plurality of nodes grouped into different classes. The classes include at least a first class of fully interconnected nodes and a second class of fully interconnected nodes, and the first class includes a source node having an information packet to be communicated to a destination node. The source node is configured to divide the information packet into segments and to disperse the segments among the nodes of the first class. The nodes of the first class are configured to transmit each of said segments directly to the nodes of said second class, wherein the first class is not fully interconnected with the second class.

Abstract: An error correction code method comprises examining a validator of one of a plurality of data in a data stream at a first processing stage and directing the one of the plurality of data through at least one subsequent processing stage to a corrected output if the validator indicates an error. The method also includes directing the one of the plurality of data to the corrected output if the validator does not indicate an error.

Abstract: The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may include a semiconductor memory device, a cache memory device and a prefetch unit. The system may also include a memory bus to couple the semiconductor memory device to the prefetch unit. The system may further include a circuit coupled to the memory bus. The circuit may detect a branch instruction within the sequence of instructions, such that the branch instruction may target a loop construct. A circuit may also be contemplated herein. The circuit may include a detector coupled to detect a loop within a sequence of instructions. The circuit may also include one or more counting devices coupled to the detector. A first counting device may count a number of clock cycles associated with a set of instructions within a loop construct.