Patents by Inventor Asher Klatchko

Asher Klatchko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7529421
    Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: May 5, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Robert J. Beauchaine, Thomas E. Chabreck, Samuel C. Howells, John J. Hubbard, Asher Klatchko, Peter Pirogovsky, Robin L. Teitzel
  • Patent number: 7420710
    Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via photolithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: September 2, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Asher Klatchko, Peter Y. Pirogovsky
  • Patent number: 7034963
    Abstract: An algorithm (method) for sizing (adjusting edges 01) grayscale or dose level pixel-maps (raster images) real time for input into radiant beam lithography systems or similar dose level grayscale image rendering systems to compensate for systemic distortions such as edge bias and/or loss of linearity (i) successively assembles one or more frame matrixes of grayscale values from a parent pixel-map having edges and corners where an edge is defined by gray pixels having values between 1, 2, . . .
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: April 25, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Asher Klatchko, Samuel C. Howells, Michael A. Ward
  • Patent number: 6998217
    Abstract: Systems and methods for gray scale lithography for defining edges such as on microelectronic device patterns during integrated circuit fabrication are disclosed. Methods for critical dimension edge placement and slope enhancement utilize central pixel dose addition or modulated inner pixels. A method for gray scale lithography for defining edges of features generally comprises identifying a center pixel of a feature, exposing the general width of the feature including the identified center pixel with full doses, and enhancing the identified center pixel by exposing the identified center pixel with additional dose to accurately place the edge of the feature, whereby the edge of the feature is defined and moved by exposing the center pixel with the additional dose.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: February 14, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Jerry Martyniuk, H. Christopher Hamaker, Matthew J. Jolley, Peter Pirogovsky, Asher Klatchko, Richard E. Crandall
  • Publication number: 20060002603
    Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.
    Type: Application
    Filed: July 1, 2004
    Publication date: January 5, 2006
    Inventors: Robert Beauchaine, Thomas Chabreck, Samuel Howells, John Hubbard, Asher Klatchko, Peter Pirogovsky, Robin Teitzel
  • Publication number: 20050036175
    Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via photolithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.
    Type: Application
    Filed: June 16, 2004
    Publication date: February 17, 2005
    Inventors: Asher Klatchko, Peter Pirogovsky
  • Patent number: 6812474
    Abstract: A pattern generation method and system in which hierarchical image data (determining a pattern to be imaged on a target) is received at a graphics engine having a memory, at least one cell determining a repeated feature or set of features of the pattern is stored in the memory, and beam control data is generated in response to the image data. The image data includes residual data including at least two subroutine call commands for each cell stored in the memory. In response to each subroutine call command, the graphics engine retrieves a cell (identified by the command) from the memory, and asserts beam control data that determines a feature or feature set determined by the cell to be imaged at (or beginning at) a location on the target identified by the command. The subroutine call commands can be distributed throughout the image data, including in at least one cell to be cached as well as in the residual data.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: November 2, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Matthew J. Jolley, Asher Klatchko, Robert Marc Sills
  • Publication number: 20040131977
    Abstract: Systems and methods for gray scale lithography for defining edges such as on microelectronic device patterns during integrated circuit fabrication are disclosed. Methods for critical dimension edge placement and slope enhancement utilize central pixel dose addition or modulated inner pixels. A method for gray scale lithography for defining edges of features generally comprises identifying a center pixel of a feature, exposing the general width of the feature including the identified center pixel with full doses, and enhancing the identified center pixel by exposing the identified center pixel with additional dose to accurately place the edge of the feature, whereby the edge of the feature is defined and moved by exposing the center pixel with the additional dose.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Jerry Martyniuk, H. Christopher Hamaker, Matthew J. Jolley, Peter Pirogovsky, Asher Klatchko, Richard E. Crandall
  • Publication number: 20030107770
    Abstract: An algorithm (method) for sizing (adjusting edges of) grayscale or dose level pixel-maps (raster images) real time for input into radiant beam lithography systems or similar dose level grayscale image rendering systems to compensate for systemic distortions such as edge bias and/or loss of linearity (i) successively assembles one or more frame matrixes of grayscale values from a parent pixel-map having edges and corners where an edge is defined by gray pixels having values between 1, 2, . . .
    Type: Application
    Filed: July 11, 2001
    Publication date: June 12, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Asher Klatchko, Samuel C. Howells, Michael A. Ward
  • Publication number: 20030010937
    Abstract: A pattern generation method and system in which hierarchical image data (determining a pattern to be imaged on a target) is received at a graphics engine having a memory, at least one cell determining a repeated feature or set of features of the pattern is stored in the memory, and beam control data is generated in response to the image data. The image data includes residual data including at least two subroutine call commands for each cell stored in the memory. In response to each subroutine call command, the graphics engine retrieves a cell (identified by the command) from the memory, and asserts beam control data that determines a feature or feature set determined by the cell to be imaged at (or beginning at) a location on the target identified by the command. The subroutine call commands can be distributed throughout the image data, including in at least one cell to be cached as well as in the residual data.
    Type: Application
    Filed: July 13, 2001
    Publication date: January 16, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Matthew J. Jolley, Asher Klatchko, Robert Marc Sills