Patents by Inventor Ashesh Parikh
Ashesh Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11775852Abstract: A system may receive a cluster prediction requirement. The system may determine a first node conglomerate by sorting a first dataset into a first plurality of nodes. The system may determine a plurality of attributes by sorting a second dataset associated with the cluster prediction requirement. The system may determine a second node conglomerate for each of the plurality of attributes. A node confidence score may be assigned to each of the second plurality of nodes. The system may determine a node graph based on a comparison between the first node conglomerate and the second node conglomerate. The node graph may be iteratively modified based on a node optimization threshold value to generate a harmonized node graph. The node optimization threshold value may be based on a map confidence score allotted to the node graph.Type: GrantFiled: August 29, 2019Date of Patent: October 3, 2023Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Ashesh Parikh, Afzal Husain, Alon Arad, Suresh Aswathnarayana, Ragnar-Miguel Myhrer, Tejas Rao, Sharad Sachdev, Joshua Intriligator, Scott Andrew Alfieri
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Publication number: 20210216907Abstract: A device may receive demand data associated with a product or a service, multiple forecasting models, and multiple cost functions, and may identify primary parameters for the multiple models based on the demand data. The device may utilize a model to rank the multiple forecasting models and the multiple cost functions based on the primary parameters, and may select optimum primary parameters based on ranking the multiple forecasting models and the multiple cost functions. The device may identify secondary parameters for the multiple forecasting models based on the demand data and the optimum primary parameters. The device may select optimum secondary parameters based on ranking the multiple forecasting models and the multiple cost functions, and may select a forecasting model, from the multiple forecasting models, based on the optimum primary parameters and the optimum secondary parameters. The device may perform one or more actions based on selecting the forecasting model.Type: ApplicationFiled: January 15, 2020Publication date: July 15, 2021Inventors: Afzal HUSAIN, Suresh ASWATHNARAYANA, Ashesh PARIKH, Paolo ASTRO, Mercedes MONROY
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Publication number: 20210065031Abstract: A system may receive a cluster prediction requirement. The system may determine a first node conglomerate by sorting a first dataset into a first plurality of nodes. The system may determine a plurality of attributes by sorting a second dataset associated with the cluster prediction requirement. The system may determine a second node conglomerate for each of the plurality of attributes. A node confidence score may be assigned to each of the second plurality of nodes. The system may determine a node graph based on a comparison between the first node conglomerate and the second node conglomerate. The node graph may be iteratively modified based on a node optimization threshold value to generate a harmonized node graph. The node optimization threshold value may be based on a map confidence score allotted to the node graph.Type: ApplicationFiled: August 29, 2019Publication date: March 4, 2021Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Ashesh PARIKH, Afzal HUSAIN, Alon ARAD, Suresh ASWATHNARAYANA, Ragnar-Miguel MYHRER, Tejas RAO, Sharad SACHDEV, Joshua INTRILIGATOR, Scott Andrew ALFIERI
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Patent number: 10339251Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.Type: GrantFiled: April 24, 2017Date of Patent: July 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ashesh Parikh, Chi-Chien Ho, Thomas John Smelko, Rajni J. Aggarwal
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Patent number: 9853086Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.Type: GrantFiled: November 14, 2016Date of Patent: December 26, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Ashesh Parikh, Bradley David Sucher
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Publication number: 20170228488Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Ashesh PARIKH, Chi-Chien HO, Thomas John SMELKO, Rajni J. AGGARWAL
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Patent number: 9665675Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.Type: GrantFiled: December 8, 2014Date of Patent: May 30, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ashesh Parikh, Chi-Chien Ho, Thomas John Smelko, Rajni J. Aggarwal
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Publication number: 20170062518Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Ashesh Parikh, Bradley David Sucher
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Patent number: 9496313Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.Type: GrantFiled: May 30, 2014Date of Patent: November 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Ashesh Parikh, Bradley David Sucher
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Publication number: 20150349022Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Inventors: Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Ashesh Parikh, Bradley David Sucher
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Publication number: 20150187655Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.Type: ApplicationFiled: December 8, 2014Publication date: July 2, 2015Inventors: Ashesh PARIKH, Chi-Chien HO, Thomas John SMELKO, Rajni J. AGGARWAL
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Patent number: 8806388Abstract: A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).Type: GrantFiled: March 22, 2013Date of Patent: August 12, 2014Assignee: Texas Instruments IncorporatedInventor: Ashesh Parikh
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Patent number: 8793626Abstract: A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.Type: GrantFiled: March 22, 2013Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Ashesh Parikh, Chi-Chien Ho, Thomas John Smelko
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Publication number: 20130254725Abstract: A method of computational lithography includes collecting inline post-develop resist critical dimension (CD) data obtained from printing a test structure having resist on a substrate having a layer thereon using a mask including a set of gratings having main features and resolution assist features (RAFs) in proximity to the main features. The RAFs include a size range so that a lithography system used for the printing prints some of the RAFs, while some of the RAFs do not print. A plurality of resist kernels are determined from the post-develop resist CD data including a non-Gaussian developer etching kernel which represents a developer used for the printing and a Gaussian kernel. A resist model is generated which provides a resist image contour from an aerial image contour and the plurality of resist kernels.Type: ApplicationFiled: March 22, 2013Publication date: September 26, 2013Applicant: Texas Instruments IncorporatedInventor: ASHESH PARIKH
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Publication number: 20130254723Abstract: A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.Type: ApplicationFiled: March 22, 2013Publication date: September 26, 2013Applicant: Texas Instruments IncorporatedInventors: ASHESH PARIKH, CHI-CHIEN HO, THOMAS JOHN SMELKO
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Publication number: 20130254724Abstract: A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).Type: ApplicationFiled: March 22, 2013Publication date: September 26, 2013Applicant: Texas Instruments IncorporatedInventor: ASHESH PARIKH
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Patent number: 8394681Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.Type: GrantFiled: August 5, 2010Date of Patent: March 12, 2013Assignee: Texas Instruments IncorporatedInventors: Ashesh Parikh, Anand Seshadri
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Publication number: 20120117519Abstract: A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to forming a photomask. A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to printing a gate pattern and optionally printing an active pattern on a wafer.Type: ApplicationFiled: November 3, 2011Publication date: May 10, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Ashesh Parikh
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Publication number: 20120105046Abstract: Current mirrors have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional current minor designs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a current minor has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: Texas Instruments IncorporatedInventors: Andrew Marshall, Ashesh Parikh
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Patent number: 8015513Abstract: A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed.Type: GrantFiled: May 30, 2008Date of Patent: September 6, 2011Assignee: Texas Instruments IncorporatedInventors: Ashesh Parikh, Willie J. Yarbrough