Abstract: A method can be implemented by a first device. A first data sequence can be received and can include a first data packet and a second data packet. It can be determined that first detection of the first data packet from the first data sequence is erroneous. The first data sequence can be stored as a first buffered data sequence in a memory buffer. A second data sequence that includes the second data packet and that excludes the first data packet can be received. The second data packet can be detected from the second data sequence. The first data packet can be detected based on the first buffered data sequence and the second data packet.

Abstract: A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.

Abstract: A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.

Abstract: A method for targeted repair of a hardware component in a computing device that is part of a cloud computing system includes monitoring a plurality of hardware components in the computing device. At some point, a defective sub-component within the hardware component of the computing device is identified. In addition to the defective sub-component, the hardware component also includes at least one sub-component that is functioning properly and a spare component that can be used in place of the defective sub-component. The method also includes initiating a targeted repair action while the computing device is connected to the cloud computing system. The targeted repair action prevents the defective sub-component from being used by the computing device without preventing sub-components that are functioning properly from being used by the computing device. The targeted repair action causes the spare component to be used in place of the defective sub-component.

Abstract: A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.

Abstract: To preserve error context during a reboot of a computing device, firmware within the computing device can be configured to implement a method that includes determining where the error context is stored in volatile memory. The method can also include identifying a plurality of recorder regions in non-volatile memory that have been assigned to store the error context. The plurality of recorder regions can be disaggregated across a plurality of distinct non-volatile memory regions. The method can also include flushing the error context from a plurality of different volatile memory locations to the plurality of recorder regions in response to detecting a trigger. The flushing can occur prior to the reboot of the computing device. The method can also include restoring at least some of the error context to the volatile memory after the computing device has been rebooted.

Abstract: To preserve error context during a reboot of a computing device, firmware within the computing device can be configured to implement a method that includes determining where the error context is stored in volatile memory. The method can also include identifying a plurality of recorder regions in non-volatile memory that have been assigned to store the error context. The plurality of recorder regions can be disaggregated across a plurality of distinct non-volatile memory regions. The method can also include flushing the error context from a plurality of different volatile memory locations to the plurality of recorder regions in response to detecting a trigger. The flushing can occur prior to the reboot of the computing device. The method can also include restoring at least some of the error context to the volatile memory after the computing device has been rebooted.

Abstract: A computing system is provided, including a processor and memory storing instructions that, when executed, cause the processor to store a firmware update patch in a runtime buffer included in the memory. The runtime buffer may be accessible by firmware and an operating system of the computing system. The processor may perform a first verification check on the firmware update patch. When the firmware update patch passes the first verification check, the processor may copy the firmware update patch to a system management random access memory (SMRAM) buffer included in the memory. The SMRAM buffer may be accessible by the firmware and inaccessible by the operating system. The processor may perform a second verification check on the copy of the firmware update patch. When the copy of the firmware update patch passes the second verification check, the processor may execute the copy of the firmware update patch.

Abstract: While booting a host computing device on a cloud computing system, system firmware (such as Basic Input/Output System (BIOS) or Unified Extensible Firmware Interface (UEFI)) sends a query to a management subsystem (such as a baseboard management controller (BMC)) for updated configuration data used during a boot of the host computing device. The management subsystem sends the updated configuration data to the system firmware, and boot instructions in the system firmware compare the updated configuration data with configuration data stored on the host computing device. If the respective configuration data match, the boot instructions continue with booting the host computing device. If the configuration data do not match, then the boot instructions update the stored configuration data with the updated configuration data and then proceed to boot the host computing device.

Abstract: A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.

Abstract: A computing device, such as a server in a cloud computing system, can be configured to enable error mitigation actions to be performed when the computing device experiences a failure. The computing device includes firmware that can be configured to detect an error indication during a boot sequence of the server, determine at least one desired error mitigation action based at least in part on the error indication, and create a boot error record that identifies the at least one desired error mitigation action. The computing device also includes an operating system that can be configured to obtain the boot error record during the boot sequence and cause the at least one desired error mitigation action that is identified in the boot error record to be performed.

Abstract: While booting a host computing device on a cloud computing system, system firmware (such as Basic Input/Output System (BIOS) or Unified Extensible Firmware Interface (UEFI)) sends a query to a management subsystem (such as a baseboard management controller (BMC)) for updated configuration data used during a boot of the host computing device. The management subsystem sends the updated configuration data to the system firmware, and boot instructions in the system firmware compare the updated configuration data with configuration data stored on the host computing device. If the respective configuration data match, the boot instructions continue with booting the host computing device. If the configuration data do not match, then the boot instructions update the stored configuration data with the updated configuration data and then proceed to boot the host computing device.

Abstract: A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.

Abstract: A method for targeted repair of a hardware component in a computing device that is part of a cloud computing system includes monitoring a plurality of hardware components in the computing device. At some point, a defective sub-component within the hardware component of the computing device is identified. In addition to the defective sub-component, the hardware component also includes at least one sub-component that is functioning properly and a spare component that can be used in place of the defective sub-component. The method also includes initiating a targeted repair action while the computing device is connected to the cloud computing system. The targeted repair action prevents the defective sub-component from being used by the computing device without preventing sub-components that are functioning properly from being used by the computing device. The targeted repair action causes the spare component to be used in place of the defective sub-component.

Abstract: A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.

Abstract: A computing system is provided, including a processor and memory storing instructions that, when executed, cause the processor to store a firmware update patch in a runtime buffer included in the memory. The runtime buffer may be accessible by firmware and an operating system of the computing system. The processor may perform a first verification check on the firmware update patch. When the firmware update patch passes the first verification check, the processor may copy the firmware update patch to a system management random access memory (SMRAM) buffer included in the memory. The SMRAM buffer may be accessible by the firmware and inaccessible by the operating system. The processor may perform a second verification check on the copy of the firmware update patch. When the copy of the firmware update patch passes the second verification check, the processor may execute the copy of the firmware update patch.

Abstract: An ultrasound imaging system provides coronal and transverse images for guiding a superior temporal artery guidewire (STA guidewire) through a tortuous region of the STA to an aortic arch region for snaring by a femoral artery catheter snare and pulling through for “through and through” guidewire access. The STA guidewire includes a knob at a distal end which is advanced into a superficial temporal artery (STA) using multi-plane ultrasound guidance, and the STA guidewire is guided through the tortuous region using transverse and coronal images provided by the multi-plane ultrasound imager. The transverse and coronal images indicate the rotational direction for the wire tip to advance the knob end of the STA guidewire within the STA to the external carotid artery.

Abstract: Thienopyrazoles of formula I, their preparation, pharmaceutical compositions comprising these compounds, and their pharmaceutical uses in the treatment of disease states capable of being modulated by the inhibition of the protein kinases, in particular interleukin-2 inducible tyrosine kinase (ITK).