Patents by Inventor Ashima Dabare

Ashima Dabare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
    Patent number: 8782582
    Abstract: This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: July 15, 2014
    Assignee: Atrenta, Inc.
    Inventors: Jitendra Gupta, Ashima Dabare, Kshitiz Krishna, Sanjiv Mathur, Ravi Varadarajan