Abstract: Techniques regarding determining hyperparameters for a differentially private federated learning process are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a hyperparameter advisor component that determines a hyperparameter for a model of a differentially private federated learning process based on a defined numeric relationship between a privacy budget, a learning rate schedule, and a batch size.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: A method for determining motor velocity includes receiving motor sensor data from at least one motor sensor associated with an electric motor, the motor sensor data including a plurality of motor sensor measurements and respective time values; determining an average time value based on the respective time values for each motor sensor measurement; generating a first gain value, a second gain value, and a third gain value, the first gain value being generated based on at least the average time value; and estimating a motor velocity based on at least one motor sensor measurement, the average time value, the first gain value, the second gain value, the third gain value, and at least one previously estimated motor velocity.

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: A distributed feedback plus reflection (DFB+R) laser includes an active section, a passive section, a low reflection (LR) mirror, and an etalon. The active section includes a distributed feedback (DFB) grating and is configured to operate in a lasing mode. The passive section is coupled end to end with the active section. The LR mirror is formed on or in the passive section. The etalon includes a portion of the DFB grating, the passive section, and the LR mirror. The lasing mode of the active section is aligned to a long-wavelength edge of a reflection peak of the etalon.

Abstract: Technical solutions are described for diagnosing an input power supply providing power to a motor. A method includes: generating a sinusoidal stimulus signal; applying, using the input power supply, the sinusoidal stimulus signal to the motor; measuring a response to the sinusoidal stimulus signal; determining a degraded condition of the input power supply based on the response to the sinusoidal stimulus signal; and performing an action in response to determining the degraded condition of the input power supply.

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the invention include a computer-implemented method that uses a processor system to access a first machine learning (ML) model. The first ML model has been trained using data of a first server. A first performance metric of the first ML model is determined using data of a second server. A benefit analysis is performed to determine a benefit of the first ML server and the second ML server participating in a federated learning system, where the benefit analysis includes using the first performance metric.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

Abstract: A method, computer system, and a computer program product for information extraction is provided. The present invention may include receiving, by a handwriting detection model of an integrated system, a mixed-text document including a combination of typed text and handwritten text, where the received mixed-text document includes at least one key-value pair. The present invention may also include receiving, by the handwriting detection model of the integrated system, a first location information of at least one key from the at least one key-value pair in the received mixed-text document. The present invention may further include detecting, by the handwriting detection model of the integrated system, at least one handwritten text in the received mixed-text document based on the received first location information of the at least one key.

Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

Abstract: A method and system. Target clusterability is calculated as an average of a respective clusterability of at least one target data item comprised by a target domain. Target-side matchability is calculated as an average of a respective matchability of each target centroid of the target domain to source centroids of a source domain, wherein the source domain comprises at least one source data item. Source-side matchability is calculated as an average of a respective matchability of each source centroid of said source centroids to the target centroids. Source-target pair matchability is calculated as an average of the target-side matchability and the source-side matchability. Cross-domain clusterability between the target domain and the source domain is calculated as a linear combination of the calculated target clusterability and the calculated source-target pair matchability. The cross-domain clusterability is transferred to a device.