Patents by Inventor Ashish A. Verma

Ashish A. Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11176479
    Abstract: Methods, systems, and computer program products for cognitive disambiguation of problem-solving tasks involving a power grid are provided herein. A computer-implemented method includes capturing user feedback pertaining to relevance of remote terminal unit measurements related to a grid event through user interface interactions carried out by the user, wherein the user interface is communicatively linked to at least one computing device; automatically inferring rules related to the grid event to curate remote terminal unit measurements across iterations of analysis by recognizing irrelevant data and/or distractions in a visual display associated with the user interface, wherein said automatically inferring comprises implementing machine learning via the at least one computing device based on the user feedback; and outputting candidate solutions to a problem-solving task involving the grid based on the inferred rules, wherein said outputting is carried out by the at least one computing device.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 16, 2021
    Assignee: Utopus Insights, Inc.
    Inventors: Chumki Basu, Ashish Verma
  • Publication number: 20210305398
    Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Nazila Haratipour, Tanay Gosavi, I-Cheng Tung, Seung Hoon Sung, Ian Young, Jack Kavalieros, Uygar Avci, Ashish Verma Penumatcha
  • Publication number: 20210287094
    Abstract: A computer-implemented machine learning model training method and resulting machine learning model. One embodiment of the method may comprise receiving at a computer memory training data; and training on a computer processor a machine learning model on the received training data using a plurality of batch sizes to produce a trained processor. The training may include calculating a plurality of activations during a forward pass of the training and discarding at least some of the calculated plurality of activations after the forward pass of the training.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Inventors: Saurabh Goyal, Anamitra Roy Choudhury, Yogish Sabharwal, Ashish Verma
  • Publication number: 20210272474
    Abstract: A system is disclosed for preventing the progression of type 2 diabetes and reducing blood sugar level to a normal range in a population of patients comprising a plurality of users diagnosed with diabetes or prediabetes. The system may include at least one administrator comprising a trained medical professional and a system server. Each user has a user interface in network communication with the server. Each user receives push communications on the user interface from the server comprising medical or lifestyle advice, and wherein each user receives prompts to enter data. A virtual coaching component may provide recommendations in real time to each user through their user interface on lifestyle choices designed to prevent the progression of diabetes. The server may aggregate results and determines trend and outcomes in the aggregate and provide data for the administrator to make decisions designed to prevent the progression of diabetes in the population of users.
    Type: Application
    Filed: May 12, 2021
    Publication date: September 2, 2021
    Inventors: Christine Tinio Geronimo-Button, Terry Michael Button, Ashish Verma
  • Publication number: 20210271520
    Abstract: One embodiment provides a method, including: receiving at least one deep learning job for scheduling and running on a distributed system comprising a plurality of nodes; receiving a batch size range indicating a minimum batch size and a maximum batch size that can be utilized for running the at least one deep learning job; determining a plurality of runtime estimations for running the at least one deep learning job; creating a list of optimal combinations of (i) batch sizes and (ii) numbers of the plurality of nodes for running both (a) the at least one deep learning job and (b) current deep learning jobs; and scheduling the at least one deep-learning job at the distributed system, responsive to identifying, by utilizing the list, that the distributed system has necessary processing resources for running both (iii) the at least one deep learning job and (iv) the current deep learning jobs.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Inventors: Saurav Basu, Vaibhav Saxena, Yogish Sabharwal, Ashish Verma, Jayaram Kallapalayam Radhakrishnan
  • Publication number: 20210241169
    Abstract: Systems, computer-implemented methods, and computer program products that can facilitate switching a model training process from a ground truth training phase to an adversarial training phase based on performance of a model trained in the ground truth training phase are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analysis component that identifies a performance condition of a model trained in a model training process. The computer executable components can further comprise a trainer component that switches the model training process from a ground truth training process to an adversarial training process based on the identified performance condition.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Inventors: Sidharth Gupta, Parijat Dube, Ashish Verma
  • Publication number: 20210216902
    Abstract: Techniques regarding determining hyperparameters for a differentially private federated learning process are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a hyperparameter advisor component that determines a hyperparameter for a model of a differentially private federated learning process based on a defined numeric relationship between a privacy budget, a learning rate schedule, and a batch size.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Inventors: Colin Sutcher-Shepard, Ashish Verma, Jayaram Kallapalayam Radhakrishnan, Gegi Thomas
  • Publication number: 20210209502
    Abstract: Methods, systems, and computer program products for determining operating range of hyperparameters are provided herein. A computer-implemented method includes obtaining a machine learning model, a list of candidate values for a hyperparameter, and a dataset; performing one or more hyperparameter range trials based on the machine learning model, the list of candidate values for the hyperparameter, and the dataset; automatically determining an operating range of the hyperparameter based on the one or more hyperparameter range trials; and training the machine learning model to convergence based at least in part on the determined operating range.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Shrihari Vasudevan, Alind Khare, Koyel Mukherjee, Yogish Sabharwal, Ashish Verma
  • Publication number: 20210167182
    Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Seung Hoon SUNG, Ashish Verma PENUMATCHA, Sou-Chi CHANG, Devin MERRILL, I-Cheng TUNG, Nazila HARATIPOUR, Jack T. KAVALIEROS, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Chia-Ching LIN, Owen LOH, Shriram SHIVARAMAN, Eric Charles MATTSON
  • Publication number: 20210167073
    Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Shriram Shivaraman, Seung Hoon Sung, Ashish Verma Penumatcha, Uygar E. Avci
  • Publication number: 20210150037
    Abstract: Embodiments relate to training a machine learning model based on an iterative algorithm in a distributed, federated, private, and secure manner. Participating entities are registered in a collaborative relationship. The registered participating entities are arranged in a topology and a topological communication direction is established. Each registered participating entity receives a public additive homomorphic encryption (AHE) key and local machine learning model weights are encrypted with the received public key. The encrypted local machine learning model weights are selectively aggregated and distributed to one or more participating entities in the topology responsive to the topological communication direction. The aggregated sum of the encrypted local machine learning model weights is subjected to decryption with a corresponding private AHE key. The decrypted aggregated sum of the encrypted local machine learning model weights is shared with the registered participating entities.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 20, 2021
    Applicant: International Business Machines Corporation
    Inventors: Jayaram Kallapalayam Radhakrishnan, Gegi Thomas, Ashish Verma
  • Publication number: 20210111179
    Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Shriram SHIVARAMAN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Nazila HARATIPOUR, Uygar E. AVCI
  • Publication number: 20210034374
    Abstract: Methods, systems, and computer program products for determining optimal compute resources for distributed batch based optimization applications are provided herein. A method includes obtaining a size of an input dataset, a size of a model, and a set of batch sizes corresponding to a job to be processed using a distributed computing system; computing, based at least in part on the set of batch sizes, one or more node counts corresponding to a number of nodes that can be used for processing said job; estimating, for each given one of the node counts, an execution time to process the job based on an average computation time for a batch of said input dataset and an average communication time for said batch of said input dataset; and selecting, based at least in part on said estimating, at least one of said node counts for processing the job.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Vaibhav Saxena, Saurav Basu, Jayaram Kallapalayam Radhakrishnan, Yogish Sabharwal, Ashish Verma
  • Patent number: 10902352
    Abstract: A computer generates labels for machine learning algorithms by retrieving, from a data storage circuit, multiple label sets that contain labels that each classify data points in a corpus of data. A graph is generated that includes a plurality of edges, each edge between two respective labels from different label sets of the multiple label sets. Weights are determined for the plurality of edges based upon a consistency between data points classified by two labels connected by the edges. An algorithm is applied that groups labels from the multiple label sets based upon the weights for the plurality of edges. Data points are identified from the corpus of data that represent conflicts within the grouped labels. An electronic message is transmitted in order to present the identified data points to entities for further classification. A new label set is generated using the further classification received from the entities.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Prasanta Ghosh, Shantanu R. Godbole, Sachindra Joshi, Srujana Merugu, Ashish Verma
  • Patent number: 10886265
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 10886286
    Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Publication number: 20200410336
    Abstract: Methods, systems, and computer program products for dataset dependent low rank decomposition of neural networks are provided herein. A computer-implemented method includes obtaining a target dataset and a trained model of a neural network; providing at least a portion of the target dataset to the trained model; determining relevance of each of one or more of filters of the neural network and channels of the neural network to the target dataset based on the provided portion, wherein the one or more of the filters and the channels correspond to at least one layer of the neural network; and compressing the trained model of the neural network based at least in part on the determined relevancies.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Anamitra Roy Choudhury, Saurabh Goyal, Vivek Sharma, Venkatesan T. Chakaravarthy, Yogish Sabharwal, Ashish Verma
  • Publication number: 20200403081
    Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Seung Hoon Sung, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Matthew Metz, Michael Harper, Jack Kavalieros, Uygar Avci, Ian Young
  • Patent number: 10832353
    Abstract: Methods, systems, and computer program products for determining intermittent renewable energy penetration limits in a grid are provided herein.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 10, 2020
    Assignees: International Business Machines Corporation, Universiti Brunei Darussalam
    Inventors: Jagabondhu Hazra, Manikandan Padmanaban, Ashish Verma, Mohammad Iskandar Pg Hj Petra, Sathyajith Mathew
  • Publication number: 20200312949
    Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS