Patents by Inventor Ashish Bhargave

Ashish Bhargave has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8077810
    Abstract: An apparatus for high data throughput reception in a WLAN includes a receiving module, first and second determining modules, a generating module, and a producing module. The receiving module receives a symbol vector representing M streams of symbols transmitted via a wireless communication channel. The first determining module determines inner coded bits and extrinsic information of the inner coded bits based on the symbol vector, a channel matrix, and inner extrinsic information feedback. The second determining module determines outer coded bits and extrinsic information of the outer coded bits based on the extrinsic information of the inner coded bits, the inner coded bits, and a soft input soft output decoding process. The generating module generates the inner extrinsic information feedback based on the extrinsic information of the outer coded bits. The producing module produces decoded bits based on the outer coded bits.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: December 13, 2011
    Assignee: Broadcom Corporation
    Inventors: Christopher J. Hansen, Jason A. Trachewsky, Ashish Bhargave
  • Publication number: 20090074096
    Abstract: An apparatus for high data throughput reception in a WLAN includes a receiving module, first and second determining modules, a generating module, and a producing module. The receiving module receives a symbol vector representing M streams of symbols transmitted via a wireless communication channel. The first determining module determines inner coded bits and extrinsic information of the inner coded bits based on the symbol vector, a channel matrix, and inner extrinsic information feedback. The second determining module determines outer coded bits and extrinsic information of the outer coded bits based on the extrinsic information of the inner coded bits, the inner coded bits, and a soft input soft output decoding process. The generating module generates the inner extrinsic information feedback based on the extrinsic information of the outer coded bits. The producing module produces decoded bits based on the outer coded bits.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: CHRISTOPHER J. HANSEN, Jason A. Trachewsky, Ashish Bhargave
  • Patent number: 7466773
    Abstract: An iterative decoder for use in a WLAN includes an inner decoder/detector, a first subtraction module, a deinterleaving module, an outer decoder, a second subtraction module, an interleaving module, and a determining module. The inner decoder/detector determines inner coded bits and extrinsic information of the inner coded bits from symbol vector based on a channel matrix and inner extrinsic information feedback. The first subtraction module subtracts the inner extrinsic information feedback from the extrinsic information of the inner coded bits. The deinterleaving module deinterleaves the output of the first subtraction module to produce deinterleaved inner extrinsic information. The outer decoder determines outer coded bits and extrinsic information of the outer coded bits from the deinterleaved inner extrinsic information. The second subtraction module subtracts the deinterleaved inner extrinsic information from the extrinsic information of the outer coded bits.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: December 16, 2008
    Assignee: Broadcom Corporation
    Inventors: Christopher J. Hansen, Jason A. Trachewsky, Ashish Bhargave
  • Publication number: 20050185739
    Abstract: An iterative decoder for use in a WLAN includes an inner decoder/detector, a first subtraction module, a deinterleaving module, an outer decoder, a second subtraction module, an interleaving module, and a determining module. The inner decoder/detector determines inner coded bits and extrinsic information of the inner coded bits from symbol vector based on a channel matrix and inner extrinsic information feedback. The first subtraction module subtracts the inner extrinsic information feedback from the extrinsic information of the inner coded bits. The deinterleaving module deinterleaves the output of the first subtraction module to produce deinterleaved inner extrinsic information. The outer decoder determines outer coded bits and extrinsic information of the outer coded bits from the deinterleaved inner extrinsic information. The second subtraction module subtracts the deinterleaved inner extrinsic information from the extrinsic information of the outer coded bits.
    Type: Application
    Filed: June 24, 2004
    Publication date: August 25, 2005
    Inventors: Christopher Hansen, Jason Trachewsky, Ashish Bhargave