Patents by Inventor Ashish Bodke
Ashish Bodke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170104031Abstract: Provided are selector elements with active components comprising insulating matrices and mobile ions disposed within these insulating matrices. Also provided are methods of operating such selector elements. The insulating matrices and mobile ions may be formed from different combinations of materials. For example, the insulating matrix may comprise amorphous silicon or silicon oxide, while mobile ions may be silver ions. In another example, the active component comprises copper and germanium, selenium, or tellerium, e.g., Se61Cu39, Se67Cu33, or Se56Cu44. The active component may be a multilayered structure with a variable composition throughout the structure. For example, the concentration of mobile ions may be higher in a center of the structure, away from the electrode interfaces. In some embodiments, outer layers may be formed from Ge33Se24Cu47, while the middle layer may be formed from Ge47Se29Cu24.Type: ApplicationFiled: October 6, 2016Publication date: April 13, 2017Applicant: Intermolecular, Inc.Inventors: Mark Clark, Prashant Phatak, Charlene Chen, Ashish Bodke, Salil Mujumdar, Federico Nardi, Satbir Kahlon, Sergey V. Barabash, Feihu Wang
-
Publication number: 20170062522Abstract: Provided are selector elements having snapback characteristics and non-volatile memory cells comprising such selector elements. To achieve its snapback characteristic, a selector element may include a dielectric layer comprising an alloy of two or more materials. In the same or other embodiments, the selector element may include a doped electrode, such carbon electrodes doped with silicon, germanium, and/or selenium. Concentrations of different materials forming an alloy may vary throughout the thickness of the dielectric layer. For example, the concentration of the first one alloy material may be higher in the center of the dielectric layer than near the interfaces of the dielectric layer with the electrodes. Some examples of this alloy material include germanium, indium, and aluminum. Examples of other materials in the same alloy include silicon, gallium, arsenic, and antimony. In some embodiments, the alloy is formed by three or more elements, such as indium gallium arsenic.Type: ApplicationFiled: August 12, 2016Publication date: March 2, 2017Applicant: Intermolecular, Inc.Inventors: Salil Mujumdar, Abhijit Pethe, Ashish Bodke, Kevin Kashefi
-
Patent number: 9455393Abstract: Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.Type: GrantFiled: December 28, 2015Date of Patent: September 27, 2016Assignee: Intermolecular, Inc.Inventors: Ashish Bodke, Frank Greer, Mark Clark
-
Publication number: 20160181380Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Amol Joshi, Sean Barstow, Paul Besser, Ashish Bodke, Guillaume Bouche, Nobumichi Fuchigami, Zhendong Hong, Shaoming Koh, Albert Sanghyup Lee, Salil Mujumdar, Abhijit Pethe, Mark Victor Raymond
-
Patent number: 9368721Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.Type: GrantFiled: November 25, 2014Date of Patent: June 14, 2016Assignee: Intermolecular, Inc.Inventors: Ashish Bodke, Mark Clark, Kevin Kashefi, Prashant B. Phatak
-
Patent number: 9362283Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.Type: GrantFiled: July 7, 2015Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
-
Publication number: 20160149129Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The metal layer of the selector element can include conductive materials such as metal silicides, and metal silicon nitrides. Conductive materials of the MSM may include tantalum silicide, tantalum silicon nitride, titanium silicide, titanium silicon nitride, or combinations thereof.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Inventors: Ashish Bodke, Mark Clark, Kevin Kashefi, Prashant B. Phatak, Dipankar Pramanik
-
Publication number: 20160149128Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Inventors: Ashish Bodke, Mark Clark, Kevin Kashefi, Prashant B. Phatak
-
Publication number: 20160148976Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on a silicon semiconductor layer doped with both carbon and nitrogen. The metal layer of the selector element can include conductive materials such as carbon, tungsten, titanium nitride, or combinations thereof.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: Ashish Bodke, Mark Clark, Kevin Kashefi, Prashant B. Phatak, Dipankar Pramanik
-
Diamond Like Carbon (DLC) in a Semiconductor Stack as a Selector for Non-Volatile Memory Application
Publication number: 20160141335Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a trilayer stack of diamond like carbon/silicon/diamond like carbon. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.Type: ApplicationFiled: November 18, 2014Publication date: May 19, 2016Inventors: Ashish Bodke, Mark Clark, Kevin Kashefi, Prashant B. Phatak -
Publication number: 20160133819Abstract: Provided are superconducting circuits and methods of forming such circuits. A circuit may include a silicon containing low loss dielectric (LLD) layer formed by fluorine passivation of dangling bonds of silicon atoms in the layer. The LLD layer may be formed from silicon nitride or silicon oxide. For uniform passivation (e.g., uniform distribution of fluorine within the LLD layer), fluorine may be introduced while forming the LLD layer. For example, a fluorine containing precursor may be supplied into a deposition chamber together with a silicon containing precursor. Alternatively, the LLD layer may be formed as a stack of many thin sublayers, and each sublayer may be subjected to individual fluorine passivation. For example, low power plasma treatment or annealing in a fluorine containing environment may be used for this purpose. The concentration of fluorine in the LLD layer may be between about 0.5% atomic and 5% atomic.Type: ApplicationFiled: December 29, 2015Publication date: May 12, 2016Applicant: Intermolecular, Inc.Inventors: Frank Greer, Ashish Bodke
-
Patent number: 9337238Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.Type: GrantFiled: October 27, 2014Date of Patent: May 10, 2016Assignee: Intermolecular, Inc.Inventors: Kevin Kashefi, Ashish Bodke, Mark Clark, Prashant B. Phatak, Dipankar Pramanik
-
Publication number: 20160118440Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.Type: ApplicationFiled: October 27, 2014Publication date: April 28, 2016Inventors: Kevin Kashefi, Ashish Bodke, Mark Clark, Prashant B. Phatak, Dipankar Pramanik
-
Patent number: 9297775Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.Type: GrantFiled: May 23, 2014Date of Patent: March 29, 2016Assignee: Intermolecular, Inc.Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
-
Patent number: 9246092Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.Type: GrantFiled: November 26, 2014Date of Patent: January 26, 2016Assignee: Intermolecular, Inc.Inventors: Ashish Bodke, Mark Clark, Kevin Kashefi, Prashant B. Phatak, Dipankar Pramanik
-
Patent number: 9236261Abstract: Transistors having a work function layer and methods of fabricating thereof are disclosed herein. The work function layer includes aluminum and titanium layers which are deposited in separate atomic layer deposition (ALD) operations. The depositions of the titanium layers and the aluminum layers may be separated by a purge operation or even performed in different ALD chambers. The work function layer may include alternating sets of titanium layers and sets of aluminum layers, thereby forming a nanolaminate structure. As such, a ratio of titanium to aluminum may be controlled and varied as needed throughout the thickness of the work function layer. For example, the work function layer may be titanium rich at the surface facing the gate dielectric in order to reduce or prevent diffusion of aluminum into the gate dielectric.Type: GrantFiled: April 1, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Kevin Kashefi, Ashish Bodke
-
Publication number: 20150338362Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: Intermolecular Inc.Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
-
Patent number: 9196475Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.Type: GrantFiled: April 16, 2014Date of Patent: November 24, 2015Assignees: GLOBALFOUNDRIES, INC., INTERMOLECULAR, INC.Inventors: Bongki Lee, Paul Besser, Kevin Kashefi, Olov Karlsson, Ashish Bodke, Ratsamee Limdulpaiboon, Divya Pisharoty, Nobi Fuchigami
-
Publication number: 20150311206Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
-
Publication number: 20150303057Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Applicants: GLOBALFOUNDRIES, Inc., Intermolecular, Inc.Inventors: Bongki Lee, Paul Besser, Kevin Kashefi, Olov Karlsson, Ashish Bodke, Ratsamee Limdulpaiboon, Divya Pisharoty, Nobi Fuchigami