Patents by Inventor Ashish Chanana

Ashish Chanana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563078
    Abstract: Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 24, 2023
    Assignee: THE UNIVERSITY OF UTAH RESEARCH FOUNDATION
    Inventors: Berardi Sensale Rodriguez, Ashish Chanana, Steven M Blair, Vikram Deshpande, Michael A Scarpulla, Hugo Orlando Condori, Jeffrey Walling
  • Publication number: 20210288136
    Abstract: Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Inventors: Berardi Sensale-Rodriguez, Ashish Chanana, Steven M. Blair, Vikram Deshpande, Michael A. Scarpulla, Hugo Orlando Condori, Jeffrey Walling