Abstract: Techniques are described for a data recovery validation test. In examples, a processor receives a command to be included in the validation test that is configured to validate performance of an activity by a server prior to a failure to perform the activity by the server. The processor stores the validation test including the command on a memory device, and prior to the failure of the activity by the server, executes the validation test including the command responsive to an input. The processor receives results of the validation test corresponding to the command and indicating whether the server performed the activity in accordance with a standard for the activity during the validation test. The processor provides the results of the validation test in a user interface.

Abstract: Techniques are described for a data recovery validation test. In examples, a processor receives a command to be included in the validation test that is configured to validate performance of an activity by a server prior to a failure to perform the activity by the server. The processor stores the validation test including the command on a memory device, and prior to the failure of the activity by the server, executes the validation test including the command responsive to an input. The processor receives results of the validation test corresponding to the command and indicating whether the server performed the activity in accordance with a standard for the activity during the validation test. The processor provides the results of the validation test in a user interface.

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

Abstract: Techniques are described for a data recovery validation test. In examples, a processor receives a command to be included in the validation test that is configured to validate performance of an activity by a server prior to a failure to perform the activity by the server. The processor stores the validation test including the command on a memory device, and prior to the failure of the activity by the server, executes the validation test including the command responsive to an input. The processor receives results of the validation test corresponding to the command and indicating whether the server performed the activity in accordance with a standard for the activity during the validation test. The processor provides the results of the validation test in a user interface.

Abstract: Techniques are described for a data recovery validation test. In examples, a processor receives a command to be included in the validation test that is configured to validate performance of an activity by a server prior to a failure to perform the activity by the server. The processor stores the validation test including the command on a memory device, and prior to the failure of the activity by the server, executes the validation test including the command responsive to an input. The processor receives results of the validation test corresponding to the command and indicating whether the server performed the activity in accordance with a standard for the activity during the validation test. The processor provides the results of the validation test in a user interface.

Abstract: Methods and apparatuses are described for authorization of computing devices using cryptographic action tokens. Delegation request data, including an identification certificate, an identifier for a second computing device, and action constraints, are received by a delegation system from a first computing device. A cryptographic action token, including the identifier for the second computing device and the action constraints, is generated by the delegation system. The cryptographic action token is transmitted to the second computing device. An action request specifying an action, the cryptographic action token, and an identification certificate is received by a transaction server. Action data based on the action request and the action constraints are determined by the transaction server. A determination that the action data satisfies the one or more action constraints in the cryptographic action token is made by the transaction server. The action is completed by the transaction server.

Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.

Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.

Abstract: In one embodiment, the execution of instructions causes a machine to: 1) display an automated test equipment (ATE) test template selection tool; 2) upon user selection of a test template from the ATE test template selection tool, display default parameters of the selected test template; and 3) provide user access to a tool that enables a user to configure at least one hardware resource specified by the test template. In another embodiment, the execution of instructions causes a machine to A) display a tool that enables a user to configure at least one hardware resource specified by a test template for ATE; and B) upon a user's use of the tool to select a hardware resource, enable the user to configure the selected hardware resource.