Patents by Inventor Ashish DHALL
Ashish DHALL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250309192Abstract: Embodiments disclosed herein comprise a first die with a conductive pad; and a second die over the first die, where the second die has a conductive pad. In an embodiment, the conductive pad of the first die is in direct contact with the conductive pad of the second die. In an embodiment, a layer is above the first die, and the second die is embedded in the layer. In an embodiment, the layer comprises an organic dielectric material. In an embodiment, a via is through the layer, and the via is electrically coupled to the first die. In an embodiment, the via comprises substantially vertical sidewalls.Type: ApplicationFiled: March 29, 2024Publication date: October 2, 2025Inventors: Xavier F. BRUN, Trianggono S. WIDODO, Ashish DHALL, Joon Sung LEE
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Publication number: 20250293137Abstract: Microelectronic devices, assemblies, and systems include a multichip architecture having one or more integrated circuit dies over and bonded to a base die, and a metallization network over the integrated circuit die(s). A backside metallization of the integrated circuit die(s) is proximal to the metallization network and a frontside metallization of the integrated circuit die(s) is opposite a device layer from the backside metallization. A via lateral to the base die couples to the metallization network to provide an electrical routing to the backside metallization of the integrated circuit die(s) through the via and the metallization network.Type: ApplicationFiled: March 15, 2024Publication date: September 18, 2025Applicant: Intel CorporationInventors: Joe Walczyk, Ravindranath Mahajan, Kaladhar Radhakrishnan, Pooya Tadayon, Stephen Morein, Omkar Karhade, Sairam Agraharam, Ashish Dhall, Gunjan Pahlani, Holly Sawyer
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Patent number: 12327773Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: January 17, 2024Date of Patent: June 10, 2025Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20240186202Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: January 17, 2024Publication date: June 6, 2024Inventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
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Patent number: 11935805Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 12, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20230245940Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Applicant: Intel CorporationInventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
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Patent number: 11664290Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 27, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20210391232Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: INTEL CORPORATIONInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 11158558Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 29, 2016Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20210111088Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 29, 2016Publication date: April 15, 2021Applicant: INTEL CORPORATIONInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 10269695Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.Type: GrantFiled: May 26, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
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Publication number: 20170287799Abstract: A stiffener, an IC package and methods of fabrication of an IC package including a removable stiffener are shown. A removable stiffener for use with an integrated circuit (IC), including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Such a removable stiffener including at least one removal tab is shown. An IC package including a removable stiffener including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Methods of fabrication of an IC package including a removable stiffener are shown.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Steven A. Klein, Aditya S. Vaidya, Vijay Krishnan Subramanian, Santosh Sankarasubramanian, Pramod Malatkar, Suriyakala Suriya Ramalingam, Ashish Dhall
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Publication number: 20170263517Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
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Patent number: 9691675Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.Type: GrantFiled: December 22, 2015Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
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Publication number: 20170178988Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
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Publication number: 20160268213Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.Type: ApplicationFiled: March 9, 2015Publication date: September 15, 2016Inventors: Hongjin JIANG, Robert STARKSTON, Digvijay A. RAORANE, Keith D. JONES, Ashish DHALL, Omkar G. KARHADE, Kedar DHANE, Suriyakala RAMALINGAM, Li-Sheng WENG, Robert F. CHENEY, Patrick N. STOVER